Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 8110897 | Semiconductor device with carbon-containing region The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in ... | 02/07/2012 |
| 8093684 | Iron sulfide semiconductor doped with Mg or Zn, junction devices and photoelectric converter comprising same The semiconductor of the present invention has iron sulfide and a forbidden band control element contained in the iron sulfide. The forbidden band control element has a property capable of controlling the forbidden band of iron sulfide on the basis of the number den... | 01/10/2012 |
| 8080863 | Semiconductor device and method of manufacturing the same A conventional semiconductor device, for example, a lateral PNP transistor has a problem that it is difficult to obtain a desired current-amplification factor while maintaining a breakdown voltage characteristic without increasing the device size. In a semiconductor... | 12/20/2011 |
| 8053867 | Phosphorous-comprising dopants and methods for forming phosphorous-doped regions in semiconductor substrates using phosphorous-comprising dopants Phosphorous-comprising dopants, methods for forming phosphorous-doped regions in a semiconductor material, and methods for fabricating phosphorous-comprising dopants are provided. In one embodiment, a phosphorous-comprising dopant comprises a phosphorous source comp... | 11/08/2011 |
| 7989923 | Bi-directional transient voltage suppression device and forming method thereof A bidirectional transient voltage suppression device is disclosed. The bi-directional transient voltage suppression device comprises a semiconductor die. The semiconductor die has a multi-layer structure comprising a semiconductor substrate of a first conductivity t... | 08/02/2011 |
| 7982289 | Wafer and a method for manufacturing a wafer A wafer includes a wafer frontside and a region adjacent to the device surface, wherein the region includes vacancy-oxygen complexes and the wafer frontside includes a predetermined surface structure to form thereon a device with a desired property. ... | 07/19/2011 |
| 7834422 | Implanted counted dopant ions This invention concerns semiconductor devices of the general type comprising a counted number of dopant atoms (142) implanted in regions of a substrate (158) that are substantially intrinsic semiconductor. One or more doped surface regions (152)... | 11/16/2010 |
| 7808080 | Synergistcally doped potassium niobate The present invention provides a photorefractive potassium niobate (KNbO3 ) crystal including a first impurity added substitutionally to the niobium (Nb) site and a second impurity added substitutionally to the potassium (K) site, wherein the first and se... | 10/05/2010 |
| 7723825 | Semiconductor device and method of manufacturing the same According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is for... | 05/25/2010 |
| 7667297 | Method for producing a stop zone in a semiconductor body and semiconductor component having a stop zone A method for producing a buried stop zone in a semiconductor body and a semiconductor component having a stop zone, has the method steps of: providing a semiconductor body having a first and a second side and a basic doping of a fi... | 02/23/2010 |
| 7615847 | Method for producing a semiconductor component A semiconductor component having a semiconductor body having first and second semiconductor regions of a first conduction type, and a third semiconductor region of a second conduction type, which is complementary to the first conduction type. The second semiconducto... | 11/10/2009 |
| 7514763 | Semiconductor device and manufacturing method for the same A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region inclu... | 04/07/2009 |
| 7378330 | Cleaving process to fabricate multilayered substrates using low implantation doses A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of ... | 05/27/2008 |
| 7378325 | Semiconductor device and manufacturing method thereof A high voltage semiconductor device having a high current gain hFE is formed with a collector region (20) of a first conduction type, an emitter region (40) of the first conduction type, and a base region (30) of a second conduction type opposit... | 05/27/2008 |
| 7361970 | Method for production of a buried stop zone in a semiconductor component and semiconductor component comprising a buried stop zone A method for the production of a stop zone in a doped zone of a semiconductor body having a first side and a second side, comprises the following method steps: applying a mask having cutouts to one of the sides of the semiconductor... | 04/22/2008 |
| 7348577 | Method for controlling a vaporizer of ion implantation equipment during indium implantation process Disclosed is a method for controlling a vaporizer in ion implantation equipment during indium implantation process. The method comprises the steps of: (a) injecting a solid indium trichloride in a vaporizer; (b) raising a vaporizer temperature up to a first temperat... | 03/25/2008 |
| 7344963 | Method of reducing charging damage to integrated circuits during semiconductor manufacturing A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein t... | 03/18/2008 |
| 7345355 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 03/18/2008 |
| 7341787 | Process for producing highly doped semiconductor wafers, and dislocation-free highly doped semiconductor wafers The invention relates to a process for producing highly doped semiconductor wafers, in which at least two dopants which are electrically active and belong to the same group of the periodic system of the elements are used for the doping. The invention also relates to... | 03/11/2008 |
| 7339215 | Transistor device containing carbon doped silicon in a recess next to MDD to create strain in channel A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxia... | 03/04/2008 |
| 7316745 | High-resistance silicon wafer and process for producing the same A high-resistance silicon wafer is manufactured, in which a gettering ability and economical efficiency is excellent and an oxygen thermal donor is effectively prevented from being generated in a heat treatment for forming a circuit, which is to be implemented on th... | 01/08/2008 |
| 7301221 | Controlling diffusion in doped semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc... | 11/27/2007 |
| 7297994 | Semiconductor device having a retrograde dopant profile in a channel region An epitaxially grown channel layer is provided on a well structure after ion implantation steps and heat treatment steps are performed to establish a required dopant profile in the well structure. The channel layer may be undoped or slightly doped, as required, so t... | 11/20/2007 |
| 7297617 | Method for controlling diffusion in semiconductor regions A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements inc... | 11/20/2007 |
| 7294883 | Nonvolatile memory cells with buried channel transistors In a nonvolatile memory cell (110), the select gate transistor is formed as a buried channel transistor to increase the transistor current. ... | 11/13/2007 |
| 7274056 | Semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 09/25/2007 |
| 7271443 | Semiconductor device and manufacturing method for the same A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region inclu... | 09/18/2007 |
| 7242059 | Semiconductor device having DMOS and CMOS on single substrate A semiconductor device includes a P-type semiconductor substrate, a P-channel DMOS transistor, a CMOS transistor. The P-channel DMOS transistor is disposed on the P-type semiconductor substrate and includes a drain formed of the P-type semiconductor substrate and a ... | 07/10/2007 |
| 7232742 | Method of manufacturing a semiconductor device that includes forming a material with a high tensile stress in contact with a semiconductor film to getter impurities from the semiconductor film In a method of crystallizing a semiconductor film by introducing a metallic element that promotes crystallization, a gettering thereafter is effectively performed. A material film having a high tensile stress, typically a silicon nitride film, is formed in contact w... | 06/19/2007 |
| 7221037 | Method of manufacturing group III nitride substrate and semiconductor device The present invention provides a method of manufacturing a Group III nitride substrate that has less variations in in-plane carrier concentration and includes crystals grown at a high growth rate. The manufacturing method of the present invention includes: (i) formi... | 05/22/2007 |
| 7202146 | Process for producing doped semiconductor wafers from silicon, and the wafers produced thereby A process for producing doped semiconductor wafers from silicon, which contain an electrically active dopant, such as boron, phosphorus, arsenic or antimony, optionally are additionally doped with germanium and have a defined thermal conductivity, involves producing... | 04/10/2007 |
| 7202540 | Semiconductor memory device A drain (7) includes a lightly-doped shallow impurity region (7a) aligned with a control gate (5), and a heavily-doped deep impurity region (7b) aligned with a sidewall film (8) and doped with impurities at a concentr... | 04/10/2007 |
| 7193294 | Semiconductor substrate comprising a support substrate which comprises a gettering site A semiconductor substrate includes a support substrate 1 has gettering sites 10 for gettering impurity metal, an embedded insulating film 2 which is provided on the support substrate 1 and contains oxides of an element whose single bond e... | 03/20/2007 |
| 7187057 | Nitrogen controlled growth of dislocation loop in stress enhanced transistor Known techniques to improve metal-oxide-semiconductor field effect transistor (MOSFET) performance is to add a high stress dielectric layer to the MOSFET. The high stress dielectric layer introduces stress in the MOSFET that causes electron mobility drive current to... | 03/06/2007 |
| 7170084 | Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the e... | 01/30/2007 |
| 7169675 | Material architecture for the fabrication of low temperature transistor A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments sho... | 01/30/2007 |
| 7163866 | SOI MOSFETS exhibiting reduced floating-body effects Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device. ... | 01/16/2007 |
| 7138318 | Method of fabricating body-tied SOI transistor having halo implant region underlying hammerhead portion of gate A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion imp... | 11/21/2006 |
| 7122863 | SOI device with structure for enhancing carrier recombination and method of fabricating same A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of t... | 10/17/2006 |
| 7112516 | Fabrication of abrupt ultra-shallow junctions One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the... | 09/26/2006 |
