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| Number | Title | Issue Date |
| 8115280 | Four-terminal gate-controlled LVBJTs An integrated circuit structure includes a well region of a first conductivity type, an emitter of a second conductivity type opposite the first conductivity type over the well region, a collector of the second conductivity type over the well region and substantiall... | 02/14/2012 |
| 8058704 | Bipolar transistor A bipolar transistor, comprising a collector, a base and an emitter, in which the collector comprises a relatively heavily doped region, and a relatively lightly doped region adjacent the base, and in which the relatively heavily doped region is substantially omitte... | 11/15/2011 |
| 7898061 | Structure for performance improvement in vertical bipolar transistors A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of th... | 03/01/2011 |
| 7843039 | Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit Stress-modified device structures, methods of fabricating such stress-modified device structures, and design structures for an integrated circuit. An electrical characteristic of semiconductor devices formed on a common substrate, such as the current gains of bipola... | 11/30/2010 |
| 7701038 | High-gain vertex lateral bipolar junction transistor A lateral bipolar junction transistor having improved current gain and a method for forming the same are provided. The transistor includes a well region of a first conductivity type formed over a substrate, at least one emitter of a second conductivity type opposite... | 04/20/2010 |
| 7495313 | Germanium substrate-type materials and approach therefor Germanium circuit-type structures are facilitated. In one example embodiment, a multi-step growth and anneal process is implemented to grow Germanium (Ge) containing material, such as heteroepitaxial-Germanium, on a substrate including Silicon (Si) or Silicon-contai... | 02/24/2009 |
| 7482673 | Structure and method for bipolar transistor having non-uniform collector-base junction A bipolar transistor is provided which includes a collector region, an intrinsic base region overlying the collector region and an emitter region overlying the intrinsic base region. An extrinsic base overlies a portion of the intrinsic base region. An epitaxial spa... | 01/27/2009 |
| 7405422 | Epitaxial and polycrystalline growth of SiGeCand SiCalloy layers on Si by UHV-CVD A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique ... | 07/29/2008 |
| 7397108 | Bipolar transistor A monolithically integrated bipolar transistor has an SOI substrate, a collector region in the SOI substrate, a base layer region on top of and in contact with the collector region, and an emitter layer region on top of and in contact with the base layer region, whe... | 07/08/2008 |
| 7394113 | Self-alignment scheme for a heterojunction bipolar transistor Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop lay... | 07/01/2008 |
| 7371471 | Electromagnetic noise suppressing thin film An electromagnetic noise suppressing thin film has a structure including an inorganic insulating matrix made of oxie, nitride, fluoride, or a mixture thereof and columnar-structured particles made of a pure metal of Fe, Co, or Ni or an alloy containing at least 20 w... | 05/13/2008 |
| 7358546 | Heterobipolar transistor and method of fabricating the same The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher t... | 04/15/2008 |
| 7352030 | Semiconductor devices with buried isolation regions Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask... | 04/01/2008 |
| 7323728 | Semiconductor device Disclosed is a semiconductor device including an n+-type semiconductor layer formed on a substrate, a first n-type semiconductor layer formed on the n+-type semiconductor layer, a p-type semiconductor layer formed on the first n-type semiconduc... | 01/29/2008 |
| 7297991 | Bipolar junction transistor and fabricating method A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening ... | 11/20/2007 |
| 7262484 | Structure and method for performance improvement in vertical bipolar transistors A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of th... | 08/28/2007 |
| 7256472 | Bipolar transistor A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance. ... | 08/14/2007 |
| 7250359 | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer.... | 07/31/2007 |
| 7229874 | Method and apparatus for allowing formation of self-aligned base contacts A method and apparatus for depositing self-aligned base contacts where over-etching the emitter sidewall to undercut the emitter contact is not needed. A semiconductor structure has a T-shaped emitter contact that comprises a T-top and T-foot. The T-top acts as a ma... | 06/12/2007 |
| 7217322 | Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of... | 05/15/2007 |
| 7211144 | Pulsed nucleation deposition of tungsten layers A method of forming a tungsten nucleation layer using a sequential deposition process. The tungsten nucleation layer is formed by reacting pulses of a tungsten-containing precursor and a reducing gas in a process chamber to deposit tungsten on the substrate. Thereaf... | 05/01/2007 |
| 7211516 | Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nicke... | 05/01/2007 |
| 7205587 | Semiconductor device and method of producing the same A method of producing a semiconductor device includes the steps of: preparing a double SOI substrate, forming a deep trench, filling the deep trench, forming an opening, forming a cavity, depositing a polycrystalline silicon layer, and forming a bipolar transistor. | 04/17/2007 |
| 7201803 | Valve control system for atomic layer deposition chamber A valve control system for a semiconductor processing chamber includes a system control computer and a plurality of electrically controlled valves associated with the processing chamber. The system further includes a programmable logic controller in communication wi... | 04/10/2007 |
| 7199447 | Angled implant to improve high current operation of bipolar transistors Method and apparatus for improving the high current operation of bipolar transistors while minimizing adverse affects on high frequency response are disclosed. A local implant to increase the doping of the collector at the collector to base interface is achieved by ... | 04/03/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7141865 | Low noise semiconductor amplifier A Low Noise semiconductor amplifier structure formed from layers of differently doped semiconductor material. This structure when properly biased will amplify voltage signals applied to the input terminal (Base1 or signal-base), and provide the same signal, a... | 11/28/2006 |
| 7135721 | Heterojunction bipolar transistor having reduced driving voltage requirements The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 i... | 11/14/2006 |
| 7132325 | Test structure and methodology for semiconductor stress-induced defects and antifuse based on same test structure A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region ... | 11/07/2006 |
| 7132338 | Methods to fabricate MOSFET devices using selective deposition process In one embodiment, a method for fabricating a silicon-based device on a substrate surface is provided which includes depositing a first silicon-containing layer by exposing the substrate surface to a first process gas comprising Cl2SiH2, a germ... | 11/07/2006 |
| 7126171 | Bipolar transistor A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer... | 10/24/2006 |
| 7122879 | Bipolar transistor with high dynamic performances A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy. ... | 10/17/2006 |
| 7119382 | Heterobipolar transistor and method of fabricating the same The present invention realizes a heterobipolar transistor using a SiGeC base layer in order to improve its electric characteristics. Specifically, the distribution of carbon and boron within the base layer is controlled so that the concentration of boron is higher t... | 10/10/2006 |
| 7118995 | Yield improvement in silicon-germanium epitaxial growth A method for determining a SiGe deposition condition so as to improve yield of a semiconductor structure. Fabrication of the semiconductor structure starts with a single-crystal silicon (Si) layer. Then, first and second shallow trench isolation (STI) regions are fo... | 10/10/2006 |
| 7105997 | Field emitter devices with emitters having implanted layer Structures and methods to ease electron emission and limit outgassing so as to inhibit degradation to the electron beam of a field emitter device are described. In one method to ease such electron emission, a layer of low relative dielectric constant material is for... | 09/12/2006 |
| 7101795 | Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer A method and system to form a refractory metal layer on a substrate features nucleating a substrate using sequential deposition techniques in which the substrate is serially exposed to first and second reactive gases followed by forming a layer, employing vapor depo... | 09/05/2006 |
| 7085616 | Atomic layer deposition apparatus A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer sup... | 08/01/2006 |
| 7067383 | Method of making bipolar transistors and resulting product A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a ... | 06/27/2006 |
| 7060583 | Method for manufacturing a bipolar transistor having a polysilicon emitter In the inventive method for manufacturing a bipolar transistor having a polysilicon emitter, a collector region of a first conductivity type and, adjoining thereto, a basis region of a second conductivity type will be generated at first. At least one layer of an ins... | 06/13/2006 |
| 7049198 | Semiconductor device and method for fabricating the same An S1-yGey layer (where 0 | 05/23/2006 |
