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| Number | Title | Issue Date |
| 7902634 | Semiconductor device An n+-emitter layer arranged under an emitter electrode is formed of convex portions arranged at predetermined intervals and a main body coupled to the convex portions. A convex portion region is in contact with the emitter electrode, and a p+-... | 03/08/2011 |
| 7320906 | Thin film transistor array panel and manufacturing method thereof A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a gate insulating layer and a semiconductor layer in sequence on the gate line; depositing a lower conductive film and an upper c... | 01/22/2008 |
| 7276764 | Semiconductor device with metal wire layer masking An object of the present invention is to provide a semiconductor device capable of radiating electron-beams only to a desired region without forming a layer for restricting the radiating rays. A source electrode 22 made of aluminum prevents the generation of ... | 10/02/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7145206 | MOS field effect transistor with reduced parasitic substrate conduction A MOS field effect transistor includes an auxiliary diffusion formed in the drain region where the auxiliary diffusion has a conductivity type opposite to the drain region and is electrically shorted to the drain region. The auxiliary diffusion region forms a parasi... | 12/05/2006 |
| 7126171 | Bipolar transistor A bipolar transistor of the present invention comprises a collector layer made of an n-type semiconductor and an emitter layer made of an n-type semiconductor provided on this collector layer. A gate layer for injecting p-type carriers (holes) into the emitter layer... | 10/24/2006 |
| 7084429 | Strained semiconductor by wafer bonding with misorientation One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semicond... | 08/01/2006 |
| 6943428 | Semiconductor device including bipolar transistor and buried conductive region A semiconductor device and a method for manufacturing the device using a semiconductor substrate of a high resistance with improved Q value of a passive circuit element. Leakage current due to an impurity fluctuation, in the high resistance semiconductor substrate a... | 09/13/2005 |
| 6894367 | Vertical bipolar transistor A vertical bipolar transistor has a J-FET incorporated in an epitaxial layer. The pinch-off voltage of the J-FET is less than the collector-emitter breakdown voltage of a bipolar transistor without the J-FET. This results in a considerable increase in the collector-... | 05/17/2005 |
| 6864538 | Protection device against electrostatic discharges An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.... | 03/08/2005 |
| 6800880 | Heterojunction bipolar transistors with extremely low offset voltage and high current gain Novel heterojunction bipolar transistors (HBT's) with high current gain and extremely low offset voltage are disclosed. Owing to the insertion of spacer/δ-doped sheet/spacer at base-emitter (B-E) heterojunction in this invention, the potential spike at B-E junction... | 10/05/2004 |
| 6759694 | Semiconductor phototransistor A phototransistor structure is disclosed. A sidewall is grown on the collector side and under the base. The surface of the sidewall is formed with a sidewall contact. When the contact is connected to an external voltage, the holes accumulated at the junction of the ... | 07/06/2004 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6534801 | GaN-based high electron mobility transistor A GaN-based high electron mobility transistor (HEMT) has an undoped GaN layer where a two-dimensional electron gas layer is formed, the undoped GaN layer having a high electric resistivity enabling a pinch-off state to be obtained even when the gate bias ... | 03/18/2003 |
| 6512251 | Semiconductor switching element that blocks in both directions The semiconductor switching element blocks in both directions between a first and a second load terminal. The switching element has a field effect transistor and a bipolar transistor. The field effect transistor has a controlled gate, a source connected t... | 01/28/2003 |
| 6509625 | Guard structure for bipolar semiconductor device A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the subs... | 01/21/2003 |
| 6504232 | Integrated circuit components thereof and manufacturing method The present invention relates to a collector pin and a trench in an integrated circuit intended for high speed communication, and to a manufacturing method for these items. The collector pin is achieved by creating an area which is implantation damaged or... | 01/07/2003 |
| 6465871 | Semiconductor switching device and method of controlling a carrier lifetime in a semiconductor switching device A semiconductor layer, through which a main current flows, is so structured that a carrier life time in the semiconductor layer is ununiform in accordance with a predetermined distribution of the carrier life time. Thus, turn OFF characteristics of a semi... | 10/15/2002 |
| 6404039 | Semiconductor device with intrinsic base diffusion layer, extrinsic base diffusion layer, and common base diffusion A bipolar transistor comprising an external base diffusion layer formed on the outer circumference of an intrinsic base diffusion layer is provided with the high withstand voltage and high reliability. A intrinsic base diffusion layer is formed on the sub... | 06/11/2002 |
| 6404037 | Insulated gate bipolar transistor An insulated gate bipolar transistor having a collector electrode 3, an emitter region 6 and a base region 4 formed between the collector electrode and the emitter region, further including a channel stop region 17 spaced from the emitter region and elect... | 06/11/2002 |
| 6384433 | Voltage variable resistor from HBT epitaxial layers A voltage variable resistor formed on heterojunction bipolar transistor epitaxial material includes a current channel made on emitter material. Emitter mesas separated by a recess provide the contacts for the voltage variable resistor. Each mesa is topped... | 05/07/2002 |
| 6355971 | Semiconductor switch devices having a region with three distinct zones and their manufacture In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accord... | 03/12/2002 |
| 6281565 | Semiconductor device and method for producing the same A semiconductor device comprising an isolating layer (diffusion layer) having a deep depth which can be produced with improved productivity and a method of the same. The semiconductor device comprises a semiconductor substrate of a first conductivity type... | 08/28/2001 |
| 6252282 | Semiconductor device with a bipolar transistor, and method of manufacturing such a device The invention relates to a semiconductor device including a preferably discrete bipolar transistor with a collector region, a base region, and an emitter region which are provided with connection conductors. A known means of preventing a saturation of the... | 06/26/2001 |
| 6232642 | Semiconductor device having impurity region locally at an end of channel formation region There is provided a semiconductor device having a novel structure in which high reliability and high field effect mobility can be simultaneously achieved. In an insulated gate transistor formed on a single crystal silicon substrate, pinning regions 105 an... | 05/15/2001 |
| 6198115 | IGBT with reduced forward voltage drop and reduced switching loss The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.... | 03/06/2001 |
| 6111325 | Gettering regions and methods of forming gettering regions within a semiconductor wafer In one aspect, the invention pertains to a method of forming a gettering region within an Si semiconductor wafer, the method including: a) providing a semiconductor material wafer; b) providing a background region within the semiconductor material wafer, ... | 08/29/2000 |
| 6093955 | Power semiconductor device A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has an gold ion implant in a region of the device between two of or the two p-n junctions, which region is the base in the case of... | 07/25/2000 |
| 6048475 | Gapfill of semiconductor structure using doped silicate glasses Improved gap fill of narrow spaces is achieved by using a doped silicate glass having a dopant concentration in a bottom portion thereof which is greater than an amount which causes surface crystal growth and in an upper portion thereof having a lower dop... | 04/11/2000 |
| 5986287 | Semiconductor structure for a transistor Semiconductor structure for a transistor, having at least one doped crystalline semiconductor layer (3) consisting of a semiconductor material such as silicon or germanium which is applied onto a further crystalline layer, wherein the doped semiconductor ... | 11/16/1999 |
| 5965929 | Bipolar Silicon transistor with arsenic and phosphorous ratio A bipolar silicon transistor includes at least one emitter zone with n+ arsenic doping and with a phosphorus doping. The ratio between arsenic dopant concentration and phosphorus dopant concentration is between 10:1 and 500:1 in the at least o... | 10/12/1999 |
| 5952695 | Silicon-on-insulator and CMOS-on-SOI double film structures Silicon is formed at selected locations on a silicon-on-insulator (SOI) substrate during fabrication of selected electronic components, including resistors, capacitors, and diodes. The silicon location is defined using a patterned, removable mask, and the... | 09/14/1999 |
| 5929508 | Defect gettering by induced stress The present invention induces provides a gettering trench on the front surface of a device substrate. In one embodiment it induces stress and simultaneously forms a gettering zone 40 for gettering impurities in an integrated circuit structure. In another ... | 07/27/1999 |
| 5923070 | Semiconductor device having an element inclusion region for reducing stress caused by lattice mismatch A semiconductor device improves its electrical characteristics by reducing crystal defects in the vicinity of junction interfaces between a semiconductor layer, and a metal compound layer composed of semiconductor and metal elements, and between an epitax... | 07/13/1999 |
| 5900652 | Apparatus for the localized reduction of the lifetime of charge carriers, particularly in integrated electronic devices A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in th... | 05/04/1999 |
| 5808352 | Semiconductor apparatus having crystal defects It is an object to provide a semiconductor apparatus having both fast switching characteristics and high dielectric breakdown strength or small leakage current characteristics, as well as a process for fabricating such improved semiconductor apparatus. Th... | 09/15/1998 |
| 5773868 | Semiconductor device and method of manufacturing the same A semiconductor device having a dielectric isolation (DI) structure using an SOI substrate or the like. An active region as a main current path of the semiconductor device is sandwiched between DI grooves having a side wall substantially vertical to the m... | 06/30/1998 |
| 5672906 | Semiconductor device having defects of deep level generated by electron beam irradiation in a semiconductor substrate The present invention is provided for improving latch-up resistance in a semiconductor integrated circuit device employing CMOS structure, for preventing the photoelectric carriers from getting into the sensors and improving the afterimage characteristic ... | 09/30/1997 |
| 5659197 | Hot-carrier shield formation for bipolar transistor The present invention provides a bipolar transistor in which a lightly doped n-type hot-carrier shield extends in an epitaxial layer adjacent from a poly-emitter to an extrinsic base. This hot-carrier shield minimizes performance impairment that would oth... | 08/19/1997 |
| 5640043 | High voltage silicon diode with optimum placement of silicon-germanium layers A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa p... | 06/17/1997 |
