Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 7994611 | Bipolar transistor fabricated in a biCMOS process According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating la... | 08/09/2011 |
| 7622790 | Transistor assembly and method for manufacturing same A transistor assembly having a transistor includes a plurality of transistor regions, each of which has a vertical transistor structure having a collector semiconductor region, a base semiconductor region and an emitter semiconductor region, emitter contacting regio... | 11/24/2009 |
| 7394113 | Self-alignment scheme for a heterojunction bipolar transistor Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop lay... | 07/01/2008 |
| 7354840 | Method for opto-electronic integration on a SOI substrate According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 04/08/2008 |
| 7338848 | Method for opto-electronic integration on a SOI substrate and related structure According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer... | 03/04/2008 |
| 7339254 | SOI substrate for integration of opto-electronics with SiGe BiCMOS According to an exemplary embodiment, a structure includes a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. The structure further includes a trench formed... | 03/04/2008 |
| 7321141 | Image sensor device and manufacturing method thereof A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. T... | 01/22/2008 |
| 7319251 | Bipolar transistor A bipolar transistor formed in a substrate includes a collector, a base layer above the collector, where the base layer includes a base that is monocrystalline, and an emitter layer that is monocrystalline and above the base, where the emitter layer includes silicon... | 01/15/2008 |
| 7312110 | Methods of fabricating semiconductor devices having thin film transistors Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a mold... | 12/25/2007 |
| 7297991 | Bipolar junction transistor and fabricating method A bipolar junction transistor includes a dielectric layer formed on a predetermined region of a substrate, an opening formed in the dielectric layer and a portion of the substrate being exposed, a semiconductor layer formed on a sidewall and a bottom of the opening ... | 11/20/2007 |
| 7256472 | Bipolar transistor A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance. ... | 08/14/2007 |
| 7227222 | Semiconductor device and manufacturing method thereof The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a first conducti... | 06/05/2007 |
| 7217606 | Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS tran... | 05/15/2007 |
| 7214616 | Homojunction semiconductor devices with low barrier tunnel oxide contacts A homojunction bipolar transistor with performance characteristics similar to more costly heterojunction or retrograde base transistors. The high emitter resistivity found in prior homojunction devices is circumvented using a low work function material layer in form... | 05/08/2007 |
| 7211491 | Method of fabricating gate electrode of semiconductor device A method of fabricating a gate electrode of a semiconductor device is disclosed. A disclosed method comprises growing a silicon epitaxial layer on a silicon substrate; making at least one trench through the epitaxial layer and filling the trench with a first oxide l... | 05/01/2007 |
| 7208361 | Replacement gate process for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming a polysilicon layer on a dielectric layer, which is formed on a substrate. The polysilicon layer is etched to generate a patterned polysilicon layer with an upper surface that is ... | 04/24/2007 |
| 7199350 | Optical input device with a light source die mounted on a detecting die and manufacture method thereof A light source die of an optical input device is mounted on a detecting die of the optical input device in order to reduce the size of the optical input device. The light source die emits light to a reflective surface, and light sensing elements formed on the detect... | 04/03/2007 |
| 7190046 | Bipolar transistor having reduced collector-base capacitance Structure and method are provided for forming a bipolar transistor. As disclosed, an intrinsic base layer is provided overlying a collector layer. A low-capacitance region is disposed laterally adjacent the collector layer. The low-capacitance region includes at lea... | 03/13/2007 |
| 7183576 | Epitaxial and polycrystalline growth of SiGeCand SiCalloy layers on Si by UHV-CVD A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique ... | 02/27/2007 |
| 7183599 | CMOS image sensor having test pattern therein and method for manufacturing the same The method for manufacturing a test pattern for use in a CMOS image sensor is employed to measure a sheet resistivity of each ion implantation region, respectively. The method includes steps of: forming an FOX area on a semiconductor substrate so as to define an act... | 02/27/2007 |
| 7180159 | Bipolar transistor having base over buried insulating and polycrystalline regions A bipolar transistor in a monocrystalline semiconductor substrate (101), which has a first conductivity type and includes a surface layer (102) of the opposite conductivity type. The transistor comprises an emitter contact (110) on the surface l... | 02/20/2007 |
| 7176061 | Semiconductor device and method for manufacturing the same In manufacturing a semiconductor memory, a gate oxide film, a polysilicon film and a WSi film are laminated on the major surface of a semiconductor wafer corresponding to both an element region on which a semiconductor chip is to be formed and a dicing region servin... | 02/13/2007 |
| 7173274 | Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe bas... | 02/06/2007 |
| 7170113 | Semiconductor device and method of manufacturing the same An aspect of a semiconductor device includes: a collector layer of first conductive type formed on a semiconductor substrate; a graft base layer of second conductive type formed in a surface region of the collector layer; a first base leading-out region of second co... | 01/30/2007 |
| 7163854 | Fabrication method of a semiconductor device To form a wiring electrode having excellent contact function, in covering a contact hole formed in an insulting film, a film of a wiring material comprising aluminum or including aluminum as a major component is firstly formed and on top of the film, a film having a... | 01/16/2007 |
| 7161198 | Semiconductor integrated circuit device having MOS transistor An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a par... | 01/09/2007 |
| 7157786 | Structure of a bipolar junction transistor and fabricating method thereof A method for fabricating a bipolar junction transistor on a wafer is disclosed. The wafer has a N-type doped area and a plurality of isolated structures. A protection layer is formed on the wafer and portions of the protection layer are then removed to expose portio... | 01/02/2007 |
| 7135757 | Bipolar transistor A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoinin... | 11/14/2006 |
| 7135373 | Reduction of channel hot carrier effects in transistor devices A transistor can be fabricated to exhibit reduced channel hot carrier effects. According to one aspect of the present invention, a method for fabricating a transistor structure includes implanting a first dopant into a lightly doped drain (LDD) region to form a shal... | 11/14/2006 |
| 7125785 | Mixed orientation and mixed material semiconductor-on-insulator wafer The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordanc... | 10/24/2006 |
| 7091100 | Polysilicon bipolar transistor and method of manufacturing it In the inventive method of producing a base terminal structure for a bipolar transistor, an etch stop layer is applied on a single-crystal semiconductor substrate, a poly-crystal base terminal layer is produced on the etch stop layer and an emitter window is etched ... | 08/15/2006 |
| 7087940 | Structure and method of forming bipolar transistor having a self-aligned raised extrinsic base using self-aligned etch stop layer A bipolar transistor structure and method of making the bipolar transistor are provided. The bipolar transistor includes a collector region, an intrinsic base layer overlying the collector region, and an emitter overlying the intrinsic base layer. An opened etch sto... | 08/08/2006 |
| 7042062 | Device isolation structures of semiconductor devices and manufacturing methods thereof A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a ... | 05/09/2006 |
| 7030431 | Metal gate with composite film stack A novel metal gate structure includes a gate oxide layer formed on a surface of a silicon substrate, a doped silicon layer stacked on the gate oxide layer, a CVD ultra-thin titanium nitride film deposited on the doped silicon layer, a tungsten nitride layer stacked ... | 04/18/2006 |
| 7018904 | Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer l... | 03/28/2006 |
| 7005665 | Phase change memory cell on silicon-on insulator substrate The present invention includes a method for forming a phase change material memory device and the phase change memory device produced therefrom. Specifically, the phase change memory device includes a semiconductor structure including a substrate having a first dope... | 02/28/2006 |
| 6979884 | Bipolar transistor having self-aligned silicide and a self-aligned emitter contact border The present invention provides a bipolar transistor having a raised extrinsic base silicide and an emitter contact border that are self-aligned. The bipolar transistor of the present invention exhibit reduced parasitics as compared with bipolar transistors that do n... | 12/27/2005 |
| 6974977 | Heterojunction bipolar transistor A bipolar transistor is provided which is of high reliability and high gain, and which is particularly suitable to high speed operation. The bipolar transistor operates with high accuracy and with no substantial change of collector current even upon change of collec... | 12/13/2005 |
| 6967144 | Low doped base spacer for reduction of emitter-base capacitance in bipolar transistors with selectively grown epitaxial base A bipolar transistor structure includes a collector region having a first conductivity type formed in a semiconductor substrate. A base region is formed over the collector region; the base region includes a highly doped lower layer having a second conductivity type ... | 11/22/2005 |
| 6960820 | Bipolar transistor self-alignment with raised extrinsic base extension and methods of forming same A self-aligned bipolar transistor structure having a raised extrinsic base comprising an outer region and an inner region of different doping concentrations and methods of fabricating the transistor are disclosed. More specifically, the self-alignment of the extrins... | 11/01/2005 |
