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| Number | Title | Issue Date |
| 7372084 | Low power bipolar transistors with low parasitic losses Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the... | 05/13/2008 |
| 7368765 | Bipolar transistors with low parasitic losses Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. Th... | 05/06/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7271414 | Semiconductor device and method for fabricating the same A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidew... | 09/18/2007 |
| 7129562 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 10/31/2006 |
| 7109567 | Semiconductor device and method of manufacturing such device The invention relates to a semiconductor device with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2), and a collector region (3), which are provided with respectively a first, a second, and a... | 09/19/2006 |
| 7078766 | Transistor and logic circuit on thin silicon-on-insulator wafers based on gate induced drain leakage currents A transistor structure fabricated on thin SOI is disclosed. The transistor on thin SOI has gated n+ and p+ junctions, which serve as switches turning on and off GIDL current on the surface of the junction. GIDL current will flow into the floating body and clamp its ... | 07/18/2006 |
| 7067857 | Semiconductor device having led out conductor layers, manufacturing method of the same, and semiconductor module The gist of the present invention is as follows: In a monolithic microwave integrate circuit (MMIC) using a heterojunction bipolar transistor (HBT), via holes are respectively formed from the bottom of the MMIC for the emitter, base and collector. Of the via holes, ... | 06/27/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7045881 | Electronic component with shielding and method for its production An electronic component with shielding is described. The component has a semiconductor chip with a semiconductor substrate. Disposed in a region of a rear side of the semiconductor substrate is an electrically conductive buried layer. The buried layer is connected v... | 05/16/2006 |
| 6977426 | Semiconductor device including high speed transistors and high voltage transistors disposed on a single substrate In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the fir... | 12/20/2005 |
| 6955972 | Methods of fabricating integrated circuit devices having trench isolation structures Methods of fabricating integrated circuit devices include forming a trench in a face of an integrated circuit substrate. The trench has a trench sidewall and a trench floor. The method further including forming a first insulating layer on the trench sidewall that ex... | 10/18/2005 |
| 6924535 | Semiconductor device with high and low breakdown voltage transistors A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semico... | 08/02/2005 |
| 6838713 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 01/04/2005 |
| 6806555 | Semiconductor component and method for fabricating it A semiconductor component and a method for fabricating it includes a substrate and an epitaxial layer situated thereon and integrating at least a first and a second bipolar component in the layer. The first and second bipolar components have a buried layer and diffe... | 10/19/2004 |
| 6777782 | Method for fabricating base-emitter self-aligned heterojunction bipolar transistors A transistor and method for making the same are disclosed. The transistor is constructed from a collector layer, a base layer, and an emitter layer in a stacked arrangement. The emitter layer is etched to form a mesa on an etched surface, the mesa having a top surfa... | 08/17/2004 |
| 6770947 | Laser-breakable fuse link with alignment and break point promotion structures A severable horizontal portion of a fuse link is formed relative to a vertically configured structure in an IC to promote separation of the severable portion upon applying energy from a laser beam. The vertically configured structure may be a reduced vertical thickn... | 08/03/2004 |
| 6703687 | Bipolar transistor and method for manufacturing the same A bipolar transistor and a method for manufacturing the bipolar transistor are provided. The bipolar transistor includes a collector region including a semiconductor substrate doped with a first conductive dopant, an intrinsic base region low-density dope... | 03/09/2004 |
| 6489665 | Lateral bipolar transistor A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral ... | 12/03/2002 |
| 6414370 | Semiconductor circuit preventing electromagnetic noise A semiconductor circuit or a semiconductor device has the current-voltage characteristic that, in a blocking-state of the semiconductor circuit or the semiconductor device, a current gently flows for values of a voltage equal to or greater than a first vo... | 07/02/2002 |
| 6335558 | Complementary bipolar/CMOS epitaxial structure and method An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded i... | 01/01/2002 |
| 6326674 | Integrated injection logic devices including injection regions and tub or sink regions A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral... | 12/04/2001 |
| 6222250 | Bipolar transistor device and method for manufacturing the same A semiconductor device is provided in which a vertical NPN transistor and a vertical PNP transistor electrically isolated from each other are formed on a p-type semiconductor substrate. An n-type buried separating region of the vertical PNP transistor is ... | 04/24/2001 |
| 6218725 | Bipolar transistors with isolation trenches to reduce collector resistance A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate... | 04/17/2001 |
| 6166426 | Lateral bipolar transistors and systems using such A substantially concentric lateral bipolar transistor and the method of forming same. A base region is disposed about a periphery of an emitter region, and a collector region is disposed about a periphery of the base region to form the concentric lateral ... | 12/26/2000 |
| 6140694 | Field isolated integrated injection logic gate An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide ("FOX"), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between t... | 10/31/2000 |
| 6137154 | Bipolar transistor with increased early voltage An improved bipolar transistor (202) has an increased Early voltage and can be integrated on a semiconductor die with MOS transistors (201) and other types of devices to form an integrated circuit (200). A p-type base region (240) is disposed in an n-type... | 10/24/2000 |
| 6127723 | Integrated device in an emitter-switching configuration An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of th... | 10/03/2000 |
| 6049131 | Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively de... | 04/11/2000 |
| 6008524 | Integrated injection logic semiconductor device A logic circuit is formed of an I2 L cell structure in which a difference of switching speeds at every collector in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant... | 12/28/1999 |
| 6005284 | Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs... | 12/21/1999 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5693978 | Reset signal output circuit and semiconductor integrated circuit device A logic circuit (3) comprises IIL aggregates (4a, 4b, 4c) each consisting of a plurality of IIL elements. Each of the IIL aggregates (4a, 4b, 4c) is supplied with an injector current (Iinj) from an injector current source (2) through a wiring (... | 12/02/1997 |
| 5641691 | Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ ... | 06/24/1997 |
| 5481132 | Transistor with a predetermined current gain in a bipolar integrated circuit A bipolar integrated circuit with N-type wells (2) formed in a P-type substrate (1) includes in first wells, first transistors (EBC), the well of which constitutes the collector. P-type base region (7a) is formed in the first well with an N+ emitter regio... | 01/02/1996 |
| 5481130 | Semiconductor IIL device with dielectric and diffusion isolation n type epitaxial layers are formed on the main surface of a p type semiconductor substrate. A field oxide film is selectively formed in the surface of n type epitaxial layers. An n type diffusion region is formed in n type epitaxial layers positioned dire... | 01/02/1996 |
| 5378921 | Heterojunction multicollector transistor There is provided a high-speed heterojunction transistor which is excellent in heat and radiation resistances with its emitter injection efficiency improved due to heterojunction. A ଲ silicon carbide layer (44) acting as base region is grown on an &... | 01/03/1995 |
| 5376822 | Heterojunction type of compound semiconductor integrated circuit A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor... | 12/27/1994 |
| 5331198 | Semiconductor device including IIL and vertical transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . Th... | 07/19/1994 |
| 5323054 | Semiconductor device including integrated injection logic and vertical NPN and PNP transistors In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n+ -type buried layer 5 serving as an emitter of the IIL and an n+ -... | 06/21/1994 |
