Bizarre Patents
User-operated amusement apparatus for kicking the user's buttocks
An apparatus including a user-operated and controlled apparatus for self-infliction of repetitive blows to the user's buttocks by a plurality of elongated arms bearing flexible extensions that rotate under the user's control.
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| Number | Title | Issue Date |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7323763 | Semiconductor device having an improved voltage controlled oscillator A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The var... | 01/29/2008 |
| 7239007 | Bipolar transistor with divided base and emitter regions A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electricall... | 07/03/2007 |
| 7235860 | Bipolar transistor including divided emitter structure A modified bipolar transistor defined for providing a larger emitter current than a basic emitter current from a basic bipolar transistor is provided. The modified transistor has an improved emitter structure comprising plural divided sub-emitter regions electricall... | 06/26/2007 |
| 7075156 | Collector structure for electrostatic discharge protection circuits Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second... | 07/11/2006 |
| 7071500 | Semiconductor device and manufacturing method for the same A bipolar semiconductor device including a collector layer covered at a portion of an outer periphery thereof with an insulating film and having a shape extending in an upper direction and a horizontal direction, with a gap being formed between the collector layer a... | 07/04/2006 |
| 7067898 | Semiconductor device having a self-aligned base contact and narrow emitter A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielect... | 06/27/2006 |
| 7049677 | Low cost dielectric isolation method for integration of vertical power MOSFET and lateral driver devices A semiconductor device has a driver device (10) in proximity to a power device (12). In making the semiconductor device, an N+ layer (24) is formed on a substrate (22). A portion of the N+ layer is removed, substantially down to the subst... | 05/23/2006 |
| 6962842 | Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited u... | 11/08/2005 |
| 6906410 | Semiconductor device and method for manufacturing same A semiconductor device includes a power supply semiconductor chip that has a plurality of current passing electrodes and a plurality of control electrodes. Conductive plates are disposed on the current electrodes and the control electrodes, and extend to regions for... | 06/14/2005 |
| 6870242 | Method for manufacturing and structure of semiconductor device with polysilicon definition structure A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation structure formed adjacent to at least a portion of the active region, and a gate oxide formed adjacent to ... | 03/22/2005 |
| 6864538 | Protection device against electrostatic discharges An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.... | 03/08/2005 |
| 6858917 | Metal oxide semiconductor (MOS) bandgap voltage reference circuit A metal oxide semiconductor (MOS) bandgap voltage reference circuit with a plurality of dummy bipolar junction transistors (BJTs) coupled to the mismatched parasitic substrate BJTs for improving parasitic capacitance matching, thereby improving startup behavior of t... | 02/22/2005 |
| 6847062 | Semiconductor device In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 | 01/25/2005 |
| 6847063 | Semiconductor device In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, ... | 01/25/2005 |
| 6798040 | Power semiconductor switch An IGBT structure includes successive regions whose conductivities have alternating signs. The structure is dimensioned for punch-through and is provided with two buffer layers. As a result, the component becomes symmetrically blocking and is suitable as a semicondu... | 09/28/2004 |
| 6770953 | Bipolar transistor A bipolar transistor is provided in which the product of base-collector capacitance and collector resistance can be reduced through a layout optimization, which leads to an improvement of the critical transistor parameters. The bipolar transistor has an emitter form... | 08/03/2004 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6323538 | Bipolar transistor and method for fabricating the same An n-type first single crystal silicon layer is provided as collector region over a silicon substrate with a first insulating film interposed therebetween. A p-type first polysilicon layer is provided as an extension of a base region over the first single... | 11/27/2001 |
| 6281530 | LPNP utilizing base ballast resistor A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (11... | 08/28/2001 |
| 6245609 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 06/12/2001 |
| 6218725 | Bipolar transistors with isolation trenches to reduce collector resistance A bipolar transistor and a method of fabricating the same are provided which are adapted to reduce chip size and production costs. To produce the transistor, a second conductive type well region is formed in a first conductive type semiconductor substrate... | 04/17/2001 |
| 6114742 | Semiconductor device including crystal defect A photoresist pattern is formed on a field oxide film and an element forming region across the field oxide film and the element forming region such that a portion of a surface of the field oxide film and a portion of a surface of a silicon epitaxial layer... | 09/05/2000 |
| 6015982 | Lateral bipolar field effect mode hybrid transistor and method for operating the same The invention relates to a semiconductor device and a method in this device, wherein the semiconductor device operates completely or partly in lateral extension. The semiconductor device comprises at least two high-voltage lateral bipolar transistors with... | 01/18/2000 |
| 5939759 | Silicon-on-insulator device with floating collector In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into t... | 08/17/1999 |
| 5773873 | Semiconductor device having multi-emitter structure A semiconductor device having a differential amplifier circuit portion made of two multi-emitter bipolar transistors (BPT). Each multi-emitter BPT has the same number of a plurality of transistor elements each having an independent emitter electrode. Each... | 06/30/1998 |
| 5736755 | Vertical PNP power device with different ballastic resistant vertical PNP transistors Disclosed are devices having emitters having resistive emitter diffusion sections are in a radial pattern. Such devices include vertical PNP power devices. The radial pattern of holes defines resistive emitter diffusion sections between adjacent holes. Th... | 04/07/1998 |
| 5545918 | Circuit construction for controlling saturation of a transistor An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element ... | 08/13/1996 |
| 5523613 | Band gap reference power supply device A semiconductor device implemented using a transistor (Q1) including at least one emitter (E1) and a transistor (Q2) which is larger than the transistor (Q1) including n emitters (E21 to E2n) each having the same area as the emitter (E1) of the transistor... | 06/04/1996 |
| 5508551 | Current mirror with saturation limiting A transistor built on a substrate employs two collectors, an output collector and a secondary collector. The purpose of the secondary collector is to collect minority carriers at saturation and feed these minority carriers back to the input reference of a... | 04/16/1996 |
| 5455449 | Offset lattice bipolar transistor architecture An architecture for producing multiple emitter vertical bipolar transistors which substantially eliminates the starved regions found in the standard lattice architecture. An "offset lattice" design is described in which the base contact segments in adjace... | 10/03/1995 |
| 5418386 | Circuit construction for controlling saturation of a transistor An integrated circuit including a semiconductor substrate, a semiconductor layer formed on the substrate, a desired bipolar transistor formed in the semiconductor layer. First and second parasitic elements are formed in the integrated circuit. An element ... | 05/23/1995 |
| 5341021 | Bipolar transistor having an electrode structure suitable for integration A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter e... | 08/23/1994 |
| 5142349 | Self-doped high performance complementary heterojunction field effect transistor A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current fl... | 08/25/1992 |
| 5068702 | Programmable transistor An improved cell structure and method for making the same for semicustom chips which can be connected at the metalization step to form either an NPN or a PNP transistor and which has approximately the same cell size as a single PNP or NPN transistor. A ce... | 11/26/1991 |
| 4939562 | Heterojunction bipolar transistors and method of manufacture A heterojunction bipolar transistor for high power applications in the microwave and millimeter wave regions is described. The heterojunction bipolar transistor includes a substrate having disposed thereover an emitter layer comprised of doped aluminum ga... | 07/03/1990 |
| 4730127 | Method of matching currents from split collector lateral pnp transistors This relates to a method of generating at least first and second matched currents from first and second multiple collector transistors. The first transistor has a base region, a first emitter region and a plurality of collector regions. The second transis... | 03/08/1988 |
| 4649411 | Gallium arsenide bipolar ECL circuit structure A gallium arsenide integrated circuit structure is disclosed wherein each transistor has only two of three terminals exposed at the semiconductor surface, thereby decreasing both the area of the structure and parasitic wiring capacitance. A dielectric bur... | 03/10/1987 |
| 4641047 | Complex direct coupled transistor logic A logic circuit is provided having increased flexibility, increased package density over I2L circuits and improved noise immunity over ISL circuits. A first NPN multi-collector transistor has its collectors coupled wherein each provide an output signal, a... | 02/03/1987 |
| 4636653 | High voltage semi-conductor switching apparatus and method This disclosure is concerned with a novel technique for achieving higher switching speeds than emitter-open switching, with lower forward voltage drops particularly for very high current applications and at lower cost, and with freedom from reverse biased... | 01/13/1987 |
