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| Number | Title | Issue Date |
| 8049307 | Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and... | 11/01/2011 |
| 7944022 | Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and... | 05/17/2011 |
| 7719086 | Lateral insulated gate bipolar transistor having a retrograde doping profile in base region and method of manufacture thereof In a semiconductor device of the present invention, a first base region 16 is extended to a part under a gate electrode 7 while having a vertical concentration profile of an impurity that increases from the surface of a semiconductor layer 3 and... | 05/18/2010 |
| 7531888 | Integrated latch-up free insulated gate bipolar transistor A lateral Insulated Gate Bipolar Transistor (LIGBT) includes a semiconductor substrate and an anode region in the semiconductor substrate. A cathode region of a first conductivity type in the substrate is laterally spaced from the anode region, and a cathode region ... | 05/12/2009 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7301220 | Semiconductor device and method of forming a semiconductor device A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provide... | 11/27/2007 |
| 7276744 | Semiconductor device and method of manufacturing the same This invention is intended to provide an HBT capable of achieving, if the HBT is a collector-up HBT, the constriction of the emitter layer disposed directly under an external base layer, and reduction in base-emitter junction capacity, or if the HBT is an emitter-up... | 10/02/2007 |
| 7268398 | ESD protection cell with active pwell resistance control In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bia... | 09/11/2007 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7217975 | Lateral type semiconductor device A lateral semiconductor device includes: a semiconductor substrate formed on a base region therein; a plurality of emitter regions with a triangle arrangement in an upper part of the base layer and collector regions surrounding the emitter regions, respectively, apa... | 05/15/2007 |
| 7176548 | Complementary analog bipolar transistors with trench-constrained isolation diffusion A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices ... | 02/13/2007 |
| 7173320 | High performance lateral bipolar transistor A lateral bipolar transistor includes an emitter region, a base region, a collector region, and a gate disposed over the base region. A bias line is connected to the gate for applying a bias voltage thereto during operation of the transistor. The polarity of the bia... | 02/06/2007 |
| 7075156 | Collector structure for electrostatic discharge protection circuits Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second... | 07/11/2006 |
| 7067898 | Semiconductor device having a self-aligned base contact and narrow emitter A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielect... | 06/27/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 7008836 | Method to provide a triple well in an epitaxially based CMOS or BiCMOS process A method to provide a triple well in an epitaxially based CMOS or B:CMOS process comprises the step of implanting the triple well prior to the epitaxial deposition. ... | 03/07/2006 |
| 6936910 | BiCMOS technology on SOI substrates A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a ... | 08/30/2005 |
| 6911715 | Bipolar transistors and methods of manufacturing the same A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a firs... | 06/28/2005 |
| 6870242 | Method for manufacturing and structure of semiconductor device with polysilicon definition structure A method including a buried layer formed on a semiconductor substrate, an active region formed adjacent to at least a portion of the buried layer, an isolation structure formed adjacent to at least a portion of the active region, and a gate oxide formed adjacent to ... | 03/22/2005 |
| 6798040 | Power semiconductor switch An IGBT structure includes successive regions whose conductivities have alternating signs. The structure is dimensioned for punch-through and is provided with two buffer layers. As a result, the component becomes symmetrically blocking and is suitable as a semicondu... | 09/28/2004 |
| 6791155 | Stress-relieved shallow trench isolation (STI) structure and method for forming the same A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is form... | 09/14/2004 |
| 6753592 | Multi-technology complementary bipolar output using polysilicon emitter and buried power buss with low temperature processing A dual polysilicon emitter, complementary output is provided which utilizes a buried power buss. While providing these advantages, the process is not complicated. The process has the speed performance of the ASSET technology with an easier process to produce. In add... | 06/22/2004 |
| 6737724 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device including a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region fo... | 05/18/2004 |
| 6703685 | Super self-aligned collector device for mono-and hetero bipolar junction transistors The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is dispo... | 03/09/2004 |
| 6570240 | Semiconductor device having a lateral bipolar transistor and method of manufacturing same In order to form a semiconductor device including a lateral bipolar transistor which is a match in the device performance for a vertical bipolar transistor, an electrically conductive film which is formed by filling a trench reaching a buried oxide film i... | 05/27/2003 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6566733 | Method and system for providing a power lateral PNP transistor using a buried power buss A power lateral PNP device is disclosed which includes an epitaxial layer; a first and second collector region embedded in the epitaxial layer; an emitter region between the first and second collector regions. Therefore slots are placed in each of the reg... | 05/20/2003 |
| 6404039 | Semiconductor device with intrinsic base diffusion layer, extrinsic base diffusion layer, and common base diffusion A bipolar transistor comprising an external base diffusion layer formed on the outer circumference of an intrinsic base diffusion layer is provided with the high withstand voltage and high reliability. A intrinsic base diffusion layer is formed on the sub... | 06/11/2002 |
| 6288427 | Silicon-germanium BiCMOS on SOI A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 μm to 0.2 μm and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 μm thick. The CMOS transisto... | 09/11/2001 |
| 6245609 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 06/12/2001 |
| 6242793 | Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar... | 06/05/2001 |
| 6225679 | Method and apparatus for protecting a device against voltage surges A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-ty... | 05/01/2001 |
| 6049131 | Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively de... | 04/11/2000 |
| 6008525 | Minority carrier device comprising a passivating layer including a Group 13 element and a chalcogenide component A minority carrier device includes at least one junction of at least two dissimilar materials, at least one of which is a semiconductor, and a passivating layer on at least one surface of the device. The passivating layer includes a Group 13 element and a... | 12/28/1999 |
| 6005284 | Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs... | 12/21/1999 |
| 6005282 | Integrated circuit with complementary isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor... | 12/21/1999 |
| 5994740 | Semiconductor device An n- -type silicon active layer having a thickness of 6 μm or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the a... | 11/30/1999 |
| 5982216 | Circuit configuration for reducing injection of minority carriers into a substrate A circuit configuration for reducing an injection of minority carriers into a substrate protects against malfunction due to injected minority carriers by providing a series circuit connected to an external terminal. The series circuit has a transistor and... | 11/09/1999 |
| 5939759 | Silicon-on-insulator device with floating collector In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into t... | 08/17/1999 |
