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| Number | Title | Issue Date |
| 7348657 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 03/25/2008 |
| 7345347 | Semiconductor device At an element formation surface side of a p-type Si substrate, a digital circuit and an analog circuit are provided. The analog circuit includes a p-type well and n-type wells formed at the element formation surface side of the p-type Si substrate. The analog circui... | 03/18/2008 |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7265434 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 09/04/2007 |
| 7138701 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 11/21/2006 |
| 7129562 | Dual-height cell with variable width power rail architecture A standard cell architecture with a basic cell that spans multiple rows of the standard cell. This multi-row basic cell may be a dual-height cell that spans two rows, or it may span more than two rows. The multi-row basic cell may be intermixed in a standard cell de... | 10/31/2006 |
| 7084041 | Bipolar device and method of manufacturing the same including pre-treatment using germane gas A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon laye... | 08/01/2006 |
| 7067899 | Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ... | 06/27/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 6992338 | CMOS transistor spacers formed in a BiCMOS process According to an exemplary method in one embodiment, a transistor gate is fabricated on a substrate. Next, an etch stop layer may be deposited on the substrate. The etch stop layer may, for example, be TEOS silicon dioxide. Thereafter, a conformal layer is deposited ... | 01/31/2006 |
| 6972476 | Diode and diode string structure A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped ... | 12/06/2005 |
| 6924535 | Semiconductor device with high and low breakdown voltage transistors A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semico... | 08/02/2005 |
| 6809396 | Integrated circuit with a high speed narrow base width vertical PNP transistor An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70... | 10/26/2004 |
| 6717235 | Semiconductor integrated circuit device having a test path The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive S... | 04/06/2004 |
| 6569730 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 05/27/2003 |
| 6537887 | Integrated circuit fabrication An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor de... | 03/25/2003 |
| 6469365 | Semiconductor component with a structure for avoiding parallel-path currents and method for fabricating a semiconductor component A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more hig... | 10/22/2002 |
| 6423590 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 07/23/2002 |
| 6265756 | Electrostatic discharge protection device An electrostatic discharge protection device for reducing electrostatic discharge spikes on a signal line is disclosed. The electrostatic discharge protection device includes first and second contact regions formed in a semiconductor material such as a co... | 07/24/2001 |
| 6245609 | High voltage transistor using P+ buried layer A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This... | 06/12/2001 |
| 6049131 | Device formed by selective deposition of refractory metal of less than 300 Angstroms of thickness A method and the device produced by the method of selective refractory metal growth/deposition on exposed silicon, but not on the field oxide is disclosed. The method includes preconditioning a wafer in a DHF dip followed by the steps of 1) selectively de... | 04/11/2000 |
| 6049118 | Circuit built-in light-receiving element A circuit built-in light-receiving element includes a buried diffusion layer of the second conductivity type, a buried diffusion layer of the first conductivity type, an epitaxial layer of the second conductivity type, a diffusion layer of the first condu... | 04/11/2000 |
| 6005282 | Integrated circuit with complementary isolated bipolar transistors Process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors. In this process an N-well is formed in a P-type substrate. P-type dopant is implanted in the N-well to become a sub-collector for a pnp transistor... | 12/21/1999 |
| 6005284 | Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs... | 12/21/1999 |
| 5976940 | Method of making plurality of bipolar transistors In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substr... | 11/02/1999 |
| 5939759 | Silicon-on-insulator device with floating collector In a semiconductor device including a silicon substrate, an insulating layer on the silicon substrate, a silicon layer on the insulating layer, the silicon layer being weakly doped with impurities of a first conduction type, a base region extending into t... | 08/17/1999 |
| 5915186 | Method of manufacturing heterojunction bipolar device having Si1-x Gex base In a semiconductor device manufacturing method for forming first and second bipolar transistors on a semiconductor substrate 1, a link base layer 5 for connecting a graft base layer (graft base layer 8) of the first bipolar transistor and an intrinsic bas... | 06/22/1999 |
| 5847440 | Bipolar transistor, semiconductor device having bipolar transistors An n-type epitaxial layer is formed on a main surface of a p-type silicon substrate. An n-type buried diffusion layer is formed extending in both the p-type silicon substrate and the n-type epitaxial layer. An n-type diffusion layer is formed in the surfa... | 12/08/1998 |
| 5838048 | Semiconductor Bi-MIS device A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are pattern... | 11/17/1998 |
| 5798560 | Semiconductor integrated circuit having a spark killer diode Buried N+ layers are formed in the surface of a substrate, on which first and second epitaxial layers are successively deposited. A vertical PNP transistor formed in the surface of the first epitaxial layer has a buried collector layer, a coll... | 08/25/1998 |
| 5641691 | Method for fabricating complementary vertical bipolar junction transistors in silicon-on-sapphire A method is described for fabricating a complementary, vertical bipolar semiconducting structure. An N+ silicon island and a P+ silicon island separated by a first oxide layer are formed on a sapphire substrate. An NPN junction device is formed on the N+ ... | 06/24/1997 |
| 5523606 | BiCMOS semiconductor device having SiGe heterojunction and Si homo-junction transistors A BiCMOS semiconductor device includes a pair of p-channel and n-channel MOS field effect transistors, a hetero-junction bipolar transistor including an epitaxial base layer made of a first compound semiconductor, and a homo-junction bipolar transistor in... | 06/04/1996 |
| 5440153 | Array architecture with enhanced routing for linear asics A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capa... | 08/08/1995 |
| 5406106 | Semiconductor Bi-MIS device and method of manufacturing the same A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar tra... | 04/11/1995 |
| 5376822 | Heterojunction type of compound semiconductor integrated circuit A heterojunction type of compound semiconductor integrated circuit in which a PNP transistor has an N type substrate made of a first compound semiconductor for mounting the PNP transistor and for insulating positive holes transmitted in the PNP transistor... | 12/27/1994 |
| 5331198 | Semiconductor device including IIL and vertical transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . Th... | 07/19/1994 |
| 5323054 | Semiconductor device including integrated injection logic and vertical NPN and PNP transistors In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n+ -type buried layer 5 serving as an emitter of the IIL and an n+ -... | 06/21/1994 |
| 5302848 | Integrated circuit with complementary junction-isolated bipolar transistors A process for making an integrated-circuit (IC) chip with junction-isolated complementary bipolar transistors, and a novel chip made by such a process. P-type dopant is implanted and diffused in an N-type substrate to form a sub-collector for a pnp transi... | 04/12/1994 |
| 5254486 | Method for forming PNP and NPN bipolar transistors in the same substrate In one embodiment, this method forms PNP and NPN transistors in a same epitaxial layer. The P-type regions for both the PNP and the NPN transistors are initially defined using a single masking step. Therefore, the emitter and collector region pattern for ... | 10/19/1993 |
