Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7432581 | Semiconductor device, method of manufacture thereof and semiconductor integrated circuit An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential... | 10/07/2008 |
| 7265018 | Method to build self-aligned NPN in advanced BiCMOS technology The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single... | 09/04/2007 |
| 7247924 | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures A method of modulating grain size in a polysilicon layer and devices fabricated with the method. The method comprises forming the layer of polysilicon on a substrate; and performing an ion implantation of a polysilicon grain size modulating species into the polysili... | 07/24/2007 |
| 7067898 | Semiconductor device having a self-aligned base contact and narrow emitter A semiconductor structure having a self-aligned base contact and an emitter, where the base contact is electrically isolated from the emitter by a dielectric layer. The separation between the base contact and the emitter is determined by the thickness of the dielect... | 06/27/2006 |
| 7026690 | Memory devices and electronic systems comprising integrated bipolar and FET devices The invention includes BIFETRAM devices. Such devices comprise a bipolar transistor in combination with a field effect transistor (FET) in a three-dimensional stacked configuration. The memory devices can be incorporated within semiconductor-on-insulator (SOI) const... | 04/11/2006 |
| 6962842 | Method of removing a sacrificial emitter feature in a BICMOS process with a super self-aligned BJT A method of removing a sacrificial emitter feature in a bipolar complementary metal oxide semiconductor (BICMOS) process with a super self-aligned bipolar junction transistor (BJT) is disclosed. According to the new method, a mask layer, such as an oxide deposited u... | 11/08/2005 |
| 6808999 | Method of making a bipolar transistor having a reduced base transit time A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening dispose... | 10/26/2004 |
| 6809353 | Method for fabricating a self-aligned bipolar transistor with planarizing layer and related structure According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises first and second link spacers situated on the top surface of the base. The bipolar transistor further comprises a sacrificial ... | 10/26/2004 |
| 6784467 | Method for fabricating a self-aligned bipolar transistor and related structure According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor further comprises a sacrificial post which, in one exemplary embodiment, is situated between first and second link spacers. The bipolar transist... | 08/31/2004 |
| 6509625 | Guard structure for bipolar semiconductor device A guard ring structure formed around the periphery of a bipolar semiconductor device. A guard region (11) is formed in a substrate (1) of the device so as to extend adjacent a peripheral portion of the device. An insulating layer (3) is formed on the subs... | 01/21/2003 |
| 6433387 | Lateral bipolar transistor Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance ... | 08/13/2002 |
| 6225679 | Method and apparatus for protecting a device against voltage surges A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-ty... | 05/01/2001 |
| 6114730 | Semiconductor device and its manufacturing method Prevents deterioration of the element characteristics of the gate voltage tolerance and the like which is caused by the metallic contaminants that are sealed in the element forming region at the time of applying a trench separator in a SOI substrate. Poly... | 09/05/2000 |
| 6104080 | Integrated circuit having capacitors for smoothing a supply voltage The integrated circuit is provided with capacitors for smoothing the supply voltage. The capacitors are disposed below the supply interconnects which supply the integrated circuit with the supply voltage. This enables the integrated circuit to be accommod... | 08/15/2000 |
| 6078088 | Low dielectric semiconductor device with rigid lined interconnection system Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. ... | 06/20/2000 |
| 6005284 | Semiconductor device and its manufacturing method A bipolar semiconductor device includes an npn transistor using a base outlet electrode in the form of a polycrystalline Si film and one or more other devices using an electrode in the form of a polycrystalline Si film supported on a common p-type Si subs... | 12/21/1999 |
| 5994740 | Semiconductor device An n- -type silicon active layer having a thickness of 6 μm or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the a... | 11/30/1999 |
| 5861640 | Mesa bipolar transistor with sub base layer A mesa bipolar transistor comprising a collector layer formed on a surface of a substrate, a base layer disposed on the substrate so as to be joined to the collector layer, an emitter layer disposed on the base layer is further provided with a sub base la... | 01/19/1999 |
| 5861659 | Semiconductor device In a semiconductor device having regions of a vertical pnp bipolar transistor, that is, a collector region composed of a p-type semiconductor region, a base region composed of an n-type semiconductor region and an emitter region composed of a p-type semic... | 01/19/1999 |
| 5856228 | Manufacturing method for making bipolar device having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 01/05/1999 |
| 5844293 | Semiconductor device with improved dielectric breakdown strength A semiconductor device is provided with improved resistance to dielectric breakdown due to high voltage resulting from static electricity applied to a dielectric film thereof, where a conductive film such as a resistance film or a electrode film is provid... | 12/01/1998 |
| 5818100 | Product resulting from selective deposition of polysilicon over single crystal silicon substrate A method, and resulting product, are disclosed for selectively forming polycrystalline silicon over exposed portions of a single crystal silicon substrate. The method includes inhibiting the formation of such polycrystalline silicon over adjacent silicon ... | 10/06/1998 |
| 5777375 | Semiconductor device improved in a structure of an L-PNP transistor A semiconductor device relating to an improvement in an L-PNP transistor in particular is such that, on a semiconductor substrate of a first conductivity type, a base region is formed which has a second conductivity type opposite in conductivity to the fi... | 07/07/1998 |
| 5708287 | Power semiconductor device having an active layer An n- -type silicon active layer having a thickness of 6 μm or less is formed on a silicon substrate via a silicon oxide film. An npn bipolar transistor with a low withstand voltage and an IGBT with a high withstand voltage are formed in the a... | 01/13/1998 |
| 5592017 | Self-aligned double poly BJT using sige spacers as extrinsic base contacts A bipolar transistor (100) and a method for forming the same. A base electrode (114) is separated from the collector region (102) by an insulator layer (110). A doped conductive spacer (115) is formed laterally adjacent the base electrode (114). The condu... | 01/07/1997 |
| 5541124 | Method for making bipolar transistor having double polysilicon structure A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor dev... | 07/30/1996 |
| 5504368 | Semiconductor integrated circuit device with self-aligned superhigh speed bipolar transistor A superhigh speed vertical transistor having an ultra thin base, a vertical NPN transistor having a reverse direction structure for composing an IIL, and a lateral PNP transistor similarly composing an injector of an IIL are integrated on a P-type silicon... | 04/02/1996 |
| 5420454 | Selective epitaxial silicon for intrinsic-extrinsic base link In a bipolar device, selective epitaxial silicon provides an improved intrinsic-extrinsic base link. A trench physically separates an intrinsic and extrinsic base portion. The trench includes sidewalls having a thin oxide layer formed thereon. The bottom ... | 05/30/1995 |
| 5397912 | Lateral bipolar transistor A lateral bipolar transistor structure (10) formed in a laterally isolated semiconductor device tub (22) of a first conductivity type is provided. First and second trenches are etched in the device tub and filled with doped polysilicon of a second conduct... | 03/14/1995 |
| 5387813 | Transistors with emitters having at least three sides A bipolar transistor is provided in which the base-emitter junctions do not traverse the base but terminate inside the top surface of the base. The transistor has long emitter perimeter available for current flow and more than two emitter sides (e.g., thr... | 02/07/1995 |
| 5355015 | High breakdown lateral PNP transistor A lateral pnp transistor for use in programmable logic arrays. The lateral pnp has a layer of oxide disposed between a polysilicon layer and the base along the base width. The oxide layer prevents diffusion of the N+ dopant contained in the polysilicon la... | 10/11/1994 |
| 5323055 | Semiconductor device with buried conductor and interconnection layer A semiconductor device includes an insulating support layer on which are mounted, in succession, a conductive layer, a buried layer comprising first and second spaced portions and a semiconductor single crystal layer comprising spaced first and second por... | 06/21/1994 |
| 5323054 | Semiconductor device including integrated injection logic and vertical NPN and PNP transistors In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n+ -type buried layer 5 serving as an emitter of the IIL and an n+ -... | 06/21/1994 |
| 5315151 | Transistor structure utilizing a deposited epitaxial base region A method of fabricating a semiconductor structure, comprising the steps of: providing a monocrystalline semiconductor device region of a first conductivity type; forming a layer of intrinsic monocrystalline semiconductor material over the device region; f... | 05/24/1994 |
| 5313090 | Bipolar memory cell having capacitors A semiconductor device including a semiconductor substrate, first and second bipolar transistors formed at the major surface of the semiconductor substrate, a Schottky-barrier diode formed on a predetermined area of each of the first and second bipolar tr... | 05/17/1994 |
| 5289024 | Bipolar transistor with diffusion compensation A bipolar transistor having a base intrinsic region, collector region, and emitter region. The emitter region, collector region, and base intrinsic region each having at least a portion thereof adjacent to an oxide isolation region. The base intrinsic reg... | 02/22/1994 |
| 5192992 | BICMOS device and manufacturing method thereof A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is im... | 03/09/1993 |
| 5162252 | Method of fabricating IIL and vertical complementary bipolar transistors The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The... | 11/10/1992 |
| 5163178 | Semiconductor device having enhanced impurity concentration profile A semiconductor device comprises a semiconductor substrate provided with a collector region a base region and an emitter region in a lateral arrangement. Respective portions having peak impurity concentrations of the collector region and the emitter regio... | 11/10/1992 |
| 5151765 | Semiconductor device comprising high-speed and high-current transistors formed in a common substrate and having matched characteristics A semiconductor device having a submicron miniaturization level structure comprises a first high-current bipolar transistor having a first wide emitter width and a second high-speed bipolar transistor having a narrow emitter width relatively to the first ... | 09/29/1992 |
