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| Number | Title | Issue Date |
| 8072043 | Semiconductor component A semiconductor component and a method for manufacturing such a semiconductor component which has a resistance behavior which depends heavily on the temperature. This resistance behavior is obtained by a special multi-layer structure of the semiconductor component, ... | 12/06/2011 |
| 7763956 | Semiconductor and method for manufacturing the same A semiconductor device and a method of fabricating same are provided. According to an embodiment, a gate insulating layer and a gate are sequentially formed on a substrate, and a pocket ion implant region is formed at sides and below a portion of the gate at a prede... | 07/27/2010 |
| 7741699 | Semiconductor device having ultra-shallow and highly activated source/drain extensions A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type sourc... | 06/22/2010 |
| 7432581 | Semiconductor device, method of manufacture thereof and semiconductor integrated circuit An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential... | 10/07/2008 |
| 7365377 | Semiconductor integrated circuit device using four-terminal transistors In a semiconductor substrate of a first conductivity type, a first well region of the first conductivity type, second well regions of a second conductivity type, and a third well region of the second conductivity type are formed. The second well regions are formed i... | 04/29/2008 |
| 7274062 | Non-volatile memory and fabricating method and operating method thereof A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrat... | 09/25/2007 |
| 7202527 | MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage to the vertical breakdown voltage A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the ... | 04/10/2007 |
| 7154142 | Non-volatile memory device and manufacturing method and operating method thereof A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type ... | 12/26/2006 |
| 7064413 | Fin-type resistors A method of forming a Fin structure including a resistor present in the thin vertically oriented semiconductor body is provided. The method includes the steps of forming at least one vertically-oriented semiconductor body having exposed vertical surfaces on a substr... | 06/20/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7002218 | Low capacitance ESD-protection structure under a bond pad An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection ... | 02/21/2006 |
| 7002222 | Integrated semiconductor memory circuit and method of manufacturing the same An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge b... | 02/21/2006 |
| 6940110 | SiC-MISFET and method for fabricating the same A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate in... | 09/06/2005 |
| 6924535 | Semiconductor device with high and low breakdown voltage transistors A semiconductor device, having a high breakdown voltage transistor and a low breakdown voltage transistor in a common substrate with different driving voltages, includes a semiconductor substrate of a first conductivity type, a first triple well formed in the semico... | 08/02/2005 |
| 6864559 | Semiconductor memory device Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory devic... | 03/08/2005 |
| 6770950 | Non-volatile semiconductor memory structure A non-volatile semiconductor memory cell structure and method of manufacture. The method includes the steps of forming a shallow first-type well layer, a second-type well layer and a deep first-type well layer over a substrate, forming stack gates over the shallow f... | 08/03/2004 |
| 6762461 | Semiconductor element protected with a plurality of zener diodes A protective circuit for protecting an IGBT from a stress due to application of an overvoltage which is induced by a surge such as static electricity is provided. The protective circuit allows for improvement in a voltage tolerance to a stress due to application of ... | 07/13/2004 |
| 6740958 | Semiconductor memory device Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory devic... | 05/25/2004 |
| 6730959 | Structure of flash memory device and fabrication method thereof A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of th... | 05/04/2004 |
| 6707115 | Transistor with minimal hot electron injection A device comprising: a layer of gate oxide on a surface of the semiconductor substrate; a gate electrode formed on the surface of the gate oxide, the gate electrode having a drain side; a p-well implanted within a semiconductor substrate under the gate electrode; an... | 03/16/2004 |
| 6614067 | Design and process for a dual gate structure A process for fabricating a polysilicon dual gate structure, featuring the use of a tungsten plug structure, used to alleviate the diode effect, present at the dopant interface in the polysilicon dual gate structure, has been developed. A first iteration ... | 09/02/2003 |
| 6563181 | High frequency signal isolation in a semiconductor device A semiconductor device (20) includes an isolated p-well (22) formed in a substrate (21) by a buried n-well (25) and an n-well ring (24). The n-well ring (24) extends from a surface of the semiconductor device (20) to the buried n-well (25). The isolated p... | 05/13/2003 |
| 6504230 | Compensation component and method for fabricating the compensation component A compensating component and a method for the production thereof are described. Compensating regions are produced by implanting sulfur or selenium in a p-conductive semiconductor layer or, are provided as p-conductive regions, which are doped with indium,... | 01/07/2003 |
| 6501147 | Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the ... | 12/31/2002 |
| 6492679 | Method for manufacturing a high voltage MOSFET device with reduced on-resistance A high voltage MOSFET device (100) has a well region (113) with two areas. The first area (110) has a high dopant concentration and the second area (112) has a low dopant concentration. Inside the well region a region of a secondary conductivity type (108... | 12/10/2002 |
| 6480639 | Optical module In an optical module having a silicon substrate, a plurality of optical semiconductor devices and optical waveguides for performing transmission of optical signals by the semiconductor devices integrated on the silicon substrate, the silicon substrate is ... | 11/12/2002 |
| 6426535 | Semiconductor device having improved short channel resistance First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impuriti... | 07/30/2002 |
| 6388298 | Detached drain MOSFET A detached drain transistor including a semiconductor substrate, a source impurity distribution, a drain impurity distribution, a gate dielectric, and a conductive gate. The source impurity distribution is substantially contained within a source region of... | 05/14/2002 |
| 6376870 | Low voltage transistors with increased breakdown voltage to substrate A high-breakdown voltage transistor (30; 30') is disclosed. The transistor (30; 30') is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed i... | 04/23/2002 |
| 6281521 | Silicon carbide horizontal channel buffered gate semiconductor devices Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a "pinched off" gate region when no bias is applied to the gate. In particular e... | 08/28/2001 |
| 6274909 | Guard ring structure with deep N well on ESD devices In this invention a deep N-type wall is created surrounding an area that contains an ESD device, or circuit. The ESD device, or circuit, is connected to a chip pad and is first surrounded by a P+ guard ring. The P+ guard ring is then surrounded by the dee... | 08/14/2001 |
| 6194776 | Semiconductor circuit device having triple-well structure in semiconductor substrate, method of fabricating the same, and mask device for fabrication of the same A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well reg... | 02/27/2001 |
| 6168983 | Method of making a high-voltage transistor with multiple lateral conduction layers A method for making a high voltage insulated gate field-effect transistor having an insulated gate field-effect device structure with a source and a drain comprises the steps of forming the drain with an extended well region having one or more buried laye... | 01/02/2001 |
| 6064077 | Integrated circuit transistor A method for fabricating an integrated circuit transistor begins with doping the substrate in the device active areas after field oxide regions have been formed. This dopant helps to reduce short channel transistor effects. A thin layer of epitaxial silic... | 05/16/2000 |
| 6028342 | ROM diode and a method of making the same A method of forming a ROM includes forming a pad oxide layer on a P-type substrate, forming a silicon nitride layer on the pad oxide layer and patterning the silicon nitride layer. An N well is formed in the P-type substrate, wherein some of the silicon n... | 02/22/2000 |
| 5942783 | Semiconductor device having improved latch-up protection A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semicondu... | 08/24/1999 |
| 5892268 | Inductive load driving and control circuits inside isolation regions A semiconductor device includes a power transistor group and a signal circuit on the same substrate. The substrate is grounded at an isolation region at an end of the substrate adjacent to the power transistor group so that the grounded portion of the sub... | 04/06/1999 |
| 5834807 | Nonvolatile memory device having an improved integration and reduced contact failure In a nonvolatile memory device and manufacturing method, the device includes cell transistors having sources and drains shared by cell transistors adjacent in a first direction, a floating gate confined to the respective cell transistors, and a control ga... | 11/10/1998 |
| 5777375 | Semiconductor device improved in a structure of an L-PNP transistor A semiconductor device relating to an improvement in an L-PNP transistor in particular is such that, on a semiconductor substrate of a first conductivity type, a base region is formed which has a second conductivity type opposite in conductivity to the fi... | 07/07/1998 |
| 5726469 | Surface voltage sustaining structure for semiconductor devices A surface voltage sustaining structure around an n+ (or p+)-type region on a p- (or n-)-type substrate for high-voltage devices is made by a combination of n-type regions and/or p-type regions and produces an ... | 03/10/1998 |
