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| Number | Title | Issue Date |
| 8164092 | PIN structures including intrinsic gallium arsenide, devices incorporating the same, and related methods Provided herein are PIN structures including a layer of amorphous n-type silicon, a layer of intrinsic GaAs disposed over the layer of amorphous n-type silicon, and a layer of amorphous p-type silicon disposed over the layer of intrinsic GaAs. The layer of intrinsic... | 04/24/2012 |
| 7741639 | Multi-chambered excimer or molecular fluorine gas discharge laser fluorine injection control A multi-chambered excimer or molecular halogen gas discharge laser system comprising at least one oscillator chamber and at least one amplifier chamber producing oscillator output laser light pulses that are amplified in the at least one power chamber, having a fluo... | 06/22/2010 |
| 7420207 | Photo-detecting device and related method of formation A photo-detecting device includes a buried doping layer of a first conductivity type and disposed at an upper portion of a silicon substrate. A first silicon epitaxial layer of first conductivity type is disposed on the buried doping layer, and a second silicon epit... | 09/02/2008 |
| 7417248 | Transistor with shallow germanium implantation region in channel A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region... | 08/26/2008 |
| 7368797 | Photoelectric conversion element and method of manufacturing the same In a back-surface electrode type photoelectric conversion element having electrodes and semiconductor layers for collecting carriers disposed only on a back surface side of a semiconductor substrate, a semiconductor thin film that is larger in band gap than the semi... | 05/06/2008 |
| 7361420 | Structure, magnetic recording medium, and method of producing the same To provide a filmy structure of a nanometer size having a phase-separated structure effective for the case where a compound can be formed between two kinds of materials. A structure constituted by a first member containing a compound between an element A except both... | 04/22/2008 |
| 7348226 | Method of forming lattice-matched structure on silicon and structure formed thereby A method (and resultant structure) of forming a semiconductor structure, includes processing an oxide to have a crystalline arrangement, and depositing an amorphous semiconductor layer on the oxide by one of evaporation and chemical vapor deposition (CVD). ... | 03/25/2008 |
| 7348620 | Forming phase change memories Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the... | 03/25/2008 |
| 7339188 | Polycrystalline silicon film containing Ni The present invention is related to a polycrystalline silicon film containing Ni which is formed by crystallizing an amorphous silicon layer containing nickel. The present invention includes a polycrystalline silicon film wherein the polycrystalline film contains Ni... | 03/04/2008 |
| 7335950 | Semiconductor device and method of making thereof To provide a thin film transistor having a low OFF characteristic and to provide P-channel type and N-channel type thin film transistors where a difference in characteristics of the P-channel type and the N-channel type thin film transistors is corrected, a region | 02/26/2008 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on... | 02/26/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7320734 | Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceil... | 01/22/2008 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7312148 | Copper barrier reflow process employing high speed optical annealing A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier met... | 12/25/2007 |
| 7312134 | Dual stressed SOI substrates The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered sta... | 12/25/2007 |
| 7303982 | Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 12/04/2007 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 12/04/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7291893 | Photoelectric conversion element and method of manufacturing the same In a back-surface electrode type photoelectric conversion element having electrodes and semiconductor layers for collecting carriers disposed only on a back surface side of a semiconductor substrate, a semiconductor thin film that is larger in band gap than the semi... | 11/06/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7282719 | Image pickup apparatus and radiation image pickup apparatus A reset method of a conversion element is improved, and the simplification of wiring and the improvement of an open area ratio of the conversion element by means of an image pickup apparatus including a plurality of pixels arranged on an insulating substrate, each o... | 10/16/2007 |
| 7279374 | Thin film transistor and method of manufacturing the same A method of manufacturing a thin film transistor is disclosed. The method includes forming an amorphous silicon layer and a blocking layer on an insulating substrate, forming a photoresist layer having first and second photoresist patterns on the blocking layer, etc... | 10/09/2007 |
| 7271333 | Apparatus and method of production of thin film photovoltaic modules The present invention relates to light-weight thin-film photovoltaic cells, methods for making cells, modules made from cells, and methods for making modules from cells. The invention teaches a manner in which individual cells may be bonded to one another, eliminati... | 09/18/2007 |
| 7262428 | Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the... | 08/28/2007 |
| 7253484 | Low-power multiple-channel fully depleted quantum well CMOSFETs A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the upperm... | 08/07/2007 |
| 7248297 | Integrated color pixel (ICP) An integrated color pixel (ICP) with at least one integrated metal filter is presented. Rather than utilizing a separate color filter, the wavelength responsivity of the ICP is specified and integrated at pixel level into the ICP itself using metal materials already... | 07/24/2007 |
| 7242006 | Dual-sided microstructured, position-sensitive detector The invention relates to a detector for determining the position and/or energy of photons and/or charged particles. Said detector comprises a plurality of diodes made of a semi-conductor material, n-contacts (1) and p-contacts (4), the n-contacts being... | 07/10/2007 |
| 7232743 | Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same A method for fabricating a semiconductor structure having a high-strained crystalline layer with a low crystal defect density is disclosed. The structure includes a substrate having a first material comprising germanium or a Group(III)-Group(V)-semiconductor or allo... | 06/19/2007 |
| 7214971 | Semiconductor light-receiving device A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the b... | 05/08/2007 |
| 7202511 | Near-infrared visible light photon counter Electromagnetic energy is detected with high efficiency in the spectral range having wavelengths of about 1–2 microns by coupling an absorber layer having high quantum efficiency in the spectral range having wavelengths of about 1–2 microns to an intrinsic semic... | 04/10/2007 |
| 7199395 | Photovoltaic cell and method of fabricating the same An i-type amorphous silicon film and an anti-reflection film made of amorphous silicon nitride or the like are formed in this order on a main surface of an n-type single-crystalline silicon substrate. On a back surface of the n-type single-crystalline silicon substr... | 04/03/2007 |
| 7195987 | Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1-x... | 03/27/2007 |
| 7196351 | Forming phase change memories Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the... | 03/27/2007 |
| 7196829 | Digital image system and method for combining sensing and image processing on sensor with two-color photo-detector A digital image system is disclosed having a sensor with an elevated two-color photo-detector for sensing two different color values in combination with a single-color photo-detector for sensing a third color value. Minimal demosaicing is performed to obtain at leas... | 03/27/2007 |
| 7183177 | Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of... | 02/27/2007 |
| 7176504 | SiGe MOSFET with an erosion preventing SiGelayer A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer ... | 02/13/2007 |
| 7166524 | Method for ion implanting insulator material to reduce dielectric constant An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielec... | 01/23/2007 |
| 7164150 | Photovoltaic device and manufacturing method thereof In a photovoltaic device of the present invention, junction characteristics are improved by enhancing interface characteristics between a crystalline silicon semiconductor and an amorphous silicon semiconductor. In the photovoltaic device, an n-type crystalline subs... | 01/16/2007 |
