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| Number | Title | Issue Date |
| 7898060 | Isolation structures for integrated circuits A variety of isolation structures for semiconductor substrates include a trench formed in the substrate that is filled with a dielectric material or filled with a conductive material and lined with a dielectric layer along the walls of the trench. The trench may be ... | 03/01/2011 |
| 7791170 | Method of making a deep junction for electrical crosstalk reduction of an image sensor The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed on the front surface of the substrate, each of the plurality of senso... | 09/07/2010 |
| 7372685 | Multi-fault protected high side switch with current sense An integrated high side switch with multi-fault protection. When a fault condition is detected, the switch is turned off. The switch includes a pair of transistors that are connected such that the source of the first transistor is connected with the source of the se... | 05/13/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7355259 | Photodiode array and optical receiver device including the same Disclosed is a photodiode array which includes a plurality of p-i-n photodiodes arrayed on a semi-insulative semiconductor substrate, each photodiode including an n-type semiconductor layer grown on the substrate, an i-type semiconductor layer grown on the n-type se... | 04/08/2008 |
| 7341901 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 03/11/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7326995 | Trench MIS device having implanted drain-drift region and thick bottom oxide A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. T... | 02/05/2008 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7275130 | Method and system for dynamically operating memory in a power-saving error correcting mode A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubb... | 09/25/2007 |
| 7256462 | Semiconductor device The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region.... | 08/14/2007 |
| 7214989 | Semiconductor device and semiconductor integrated circuit device Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. P wells and N wells are formed in a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer und... | 05/08/2007 |
| 7202527 | MOS transistor and ESD protective device each having a settable voltage ratio of the lateral breakdown voltage to the vertical breakdown voltage A MOS transistor includes a drain zone, a source zone, and a gate electrode. Doping atoms of the first conductivity type are implanted in the region of the drain zone and the source zone by at least two further implantation steps such that a pn junction between the ... | 04/10/2007 |
| 7183808 | Circuit for power management of standard cell application A power management circuit for logic cells. A logic cell is operated in normal or standby modes according to a power control signal. The logic cell includes an output terminal and a power input terminal. A switch is coupled between a power voltage, the power control... | 02/27/2007 |
| 7180132 | Enhanced RESURF HVPMOS device with stacked hetero-doping RIM and gradual drift region An HV PMOS device formed on a substrate having an HV well of a first polarity type formed in an epitaxial layer of a second polarity type includes a pair of field oxide regions on the substrate and at least partially over the HV well. Insulated gates are formed on t... | 02/20/2007 |
| 7176093 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 02/13/2007 |
| 7158404 | Power management circuit and memory cell A circuit for power management of a memory cell. A first power switch is coupled between a power voltage, the power control signal and the memory cell. The first power switch is turned off to disconnect the power voltage and the memory cell when the power control si... | 01/02/2007 |
| 7135363 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 11/14/2006 |
| 7132848 | Power management circuit A power management circuit. A logic cell switched between normal and standby modes according to a power control signal includes a plurality of first NMOS transistors coupled between at least one complementary pair of data signal inputs and a complementary pair of da... | 11/07/2006 |
| 7072237 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 07/04/2006 |
| 7071537 | Power device having electrodes on a top surface thereof A power device includes a substrate assembly including an upper surface and a lower surface. The substrate assembly includes a first layer and a second layer. The first layer overlies the second layer and has different conductivity than the second layer. A first ele... | 07/04/2006 |
| 7045405 | Semiconductor processing methods of forming integrated circuitry Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo impla... | 05/16/2006 |
| 7026704 | Semiconductor device for reducing plasma charging damage A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation ar... | 04/11/2006 |
| 7022560 | Method to manufacture high voltage MOS transistor by ion implantation A method for fabrication of a high-voltage, high-frequency MOS-transistor combines a deep n-well and a p-well process and the formation of an extended drain region (45), and a channel region (31), the channel having a short length and becoming well ali... | 04/04/2006 |
| 7011998 | High voltage transistor scaling tilt ion implant method The present invention is a high voltage transistor formation method and system that includes a varying or gradient concentration lightly doped drain and source implant region. The lightly doped drain (LDD) implant region has gradient concentration characteristics th... | 03/14/2006 |
| 7002222 | Integrated semiconductor memory circuit and method of manufacturing the same An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge b... | 02/21/2006 |
| 6979845 | Semiconductor device in which punchthrough is prevented A semiconductor device includes a semiconductor region of a first conductive type. First and second regions of a second conductive type opposite to the first conductive type are provided in a surface of the semiconductor region in a predetermined interval. A third r... | 12/27/2005 |
| 6965540 | Memory device operable in either a high-power, full-page size mode or a low-power, reduced-page size mode A memory device includes 4 memory banks each of which includes first and second arrays of memory cells. A mode register is programmed with a bit that selects a high-power, large-page operating mode or a low-power, small-page operating mode. In the high-power mode, a... | 11/15/2005 |
| 6953981 | Semiconductor device with deep substrates contacts The present invention relates to a semiconductor device arranged at a surface of a semiconductor substrate having an initial doping having an electrical connection comprising at least one plug made of a material with a high conductivity, especially a material other ... | 10/11/2005 |
| 6925021 | Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full den... | 08/02/2005 |
| 6914309 | Semiconductor device with double sidewall spacer and layered contact A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silic... | 07/05/2005 |
| 6897536 | ESD protection circuit An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the subs... | 05/24/2005 |
| 6867476 | Vertical double diffused MOSFET and method of fabricating the same In a DMOS device, a drift region is located over a substrate and is lightly doped with impurities of a first conductivity type. A plurality of body areas are located in the drift region and doped with impurities of a second conductivity type which is opposite the fi... | 03/15/2005 |
| 6847094 | Contact structure on a deep region formed in a semiconductor substrate The forming of a contact with a deep region of a first conductivity type formed in a silicon substrate. The contact includes a doped silicon well region of the first conductivity type and an intermediary region connected between the deep layer and the well. This int... | 01/25/2005 |
| 6838745 | Semiconductor device having a separation structure for high withstand voltage An n-type well is formed in a p−-type semiconductor substrate and a p−-type epitaxial layer is formed on; the n-type well. An n−-type well is formed in the, p-type epitaxial layer on the n-type well so as to allow a RESURF oper... | 01/04/2005 |
| 6835992 | Closely-spaced VCSEL and photodetector for applications requiring their independent operation A monolthically integrated VCSEL and photodetector, and a method of manufacturing same, are disclosed for applications where the VCSEL and photodetector require separate operation such as duplex serial data communications applications. A first embodiment integrates ... | 12/28/2004 |
| 6809790 | Matrix substrate, liquid crystal display device using it, and method for producing the matrix substrate A matrix substrate having, on a substrate, a plurality of electroconductive members to constitute pixel electrodes arrayed in a matrix pattern, and an electrically insulating member comprising a projecting region disposed between the electroconductive members to sep... | 10/26/2004 |
| 6784493 | Line self protecting multiple output power IC architecture A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control c... | 08/31/2004 |
| 6710427 | Distributed power device with dual function minority carrier reduction A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (5... | 03/23/2004 |
