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| Number | Title | Issue Date |
| 8115279 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion of the workpiece. An isolation ring structure is disposed within the t... | 02/14/2012 |
| 8039925 | Integrated radio frequency circuits A plurality of devices, such as devices that are utilized for implementing radio frequency applications, can be formed in the same substrate. Each of these devices may be formed over a triple well that includes at least one well capable of being biased. Each of the ... | 10/18/2011 |
| 7982288 | Semiconductor device and method of fabricating the same A semiconductor device including a substrate, a high voltage device, a medium voltage device and a low voltage device is provided. The substrate includes a high voltage circuit area, a medium voltage circuit area and a low voltage circuit area. The high voltage devi... | 07/19/2011 |
| 7977768 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the ... | 07/12/2011 |
| 7868423 | Optimized device isolation A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region undern... | 01/11/2011 |
| 7750437 | Semiconductor device having a diode for a rectifier circuit A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region an... | 07/06/2010 |
| 7443009 | N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second... | 10/28/2008 |
| 7411272 | Semiconductor device and method of forming a semiconductor device A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals co... | 08/12/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7355226 | Power semiconductor and method of fabrication This invention is generally concerned with power semiconductors such as power MOS transistors, insulated gate by bipolar transistors (IGBTs), high voltage diodes and the like, and method for their fabrication. A power semiconductor, the semiconductor comprising a po... | 04/08/2008 |
| 7345355 | Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec... | 03/18/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7306990 | Information storage element, manufacturing method thereof, and memory array An information memory device capable of reading and writing of information by mechanical operation of a floating gate layer, in which a gate insulation film has a cavity (6), and a floating gate layer (5) having two stable deflection states in the cavi... | 12/11/2007 |
| 7285823 | Superjunction semiconductor device structure In one embodiment, a charge compensation region is formed in a body of semiconductor material. A conductive layer is coupled to the charge compensation layer. In a further embodiment, the charge compensation region comprises a trench filled with opposite conductivit... | 10/23/2007 |
| 7268410 | Integrated switching voltage regulator using copper process technology Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yi... | 09/11/2007 |
| 7259428 | Semiconductor device using SOI structure having a triple-well region A semiconductor device includes a support substrate, a buried insulation film, provided on the support substrate, having a thickness of 5 to 10 nm, a silicon layer provided on the buried insulation film, a MOSFET provided in the silicon layer, and a triple-well regi... | 08/21/2007 |
| 7247533 | Method of fabricating semiconductor device using selective epitaxial growth A method of fabricating a semiconductor device uses selective epitaxial growth (SEG), by which leakage current generation is minimized using lateral SEG growth in case a contact intrudes a shallow track isolation feature. The method includes steps of forming a sidew... | 07/24/2007 |
| 7230263 | Gallium nitride compound semiconductor element In a gallium nitride semiconductor device comprising an active layer made of an n-type gallium nitride semiconductor that includes In and is doped with n-type impurity and a p-type cladding layer made of a p-type gallium nitride semiconductor that includes Al and is... | 06/12/2007 |
| 7230314 | Semiconductor device and method of forming a semiconductor device A semiconductor device having an active region is formed in a layer provided on a semiconductor substrate. At least a portion of the semiconductor substrate below at least a portion of the active region is removed such that the portion of the active region is provid... | 06/12/2007 |
| 7215206 | Stacked RF power amplifier A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be imp... | 05/08/2007 |
| 7183216 | Methods to form oxide-filled trenches A thermal oxidation process is used to fill trenches with an oxide; however, the oxidation process consumes some of the silicon. The embodiments herein advantageously apply this tendency for the oxidation process to consume silicon so as to convert all the silicon s... | 02/27/2007 |
| 7119393 | Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ... | 10/10/2006 |
| 7105875 | Lateral power diodes A lateral power diodes with an optimal drift doping formed in widebandgap semiconductors like Silicon Carbide, Aluminum Nitride and Gallium Nitride and Diamond are provided with a voltage rating greater 200V. Contrary to conventional vertical design of power diodes,... | 09/12/2006 |
| 7084030 | Method of forming a non-volatile memory device having floating trap type memory cell A non-volatile memory device includes a cell region having a memory gate pattern with a charge storage layer, and a peripheral region having a high-voltage-type gate pattern, a low-voltage-type gate pattern, and a resistor pattern. To fabricate the above memory devi... | 08/01/2006 |
| 7072374 | Ridge waveguide semiconductor laser diode A ridge waveguide semiconductor laser diode is disclosed that comprises an n-type semiconductor layer, a p-type semiconductor layer having a ridge forming a waveguide and an active layer disposed between the n-type semiconductor layer and the p-type semiconductor la... | 07/04/2006 |
| 7053718 | Stacked RF power amplifier A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be imp... | 05/30/2006 |
| 7038234 | Thermoelectric module with Si/SiGe and B4C/B9C super-lattice legs A super-lattice thermoelectric device. The device includes p-legs and n-legs, each leg having a large number of alternating layers of two materials with differing electron band gaps. The n-legs in the device are comprised of alternating layers of silicon and silicon... | 05/02/2006 |
| 7022566 | Integrated radio frequency circuits An RF circuit may be formed over a triple well that creates two reverse biased junctions. By adjusting the bias across the junctions, the capacitance across the junctions can be reduced, reducing the capacitive coupling from the RF circuits to the substrate, improvi... | 04/04/2006 |
| 7009271 | Memory device with an alternating Vss interconnection A semiconductor memory device provides non-volatile memory with a memory array having an alternating Vss interconnection. Using the alternating Vss interconnection, a low implant dosage is added to a region proximate to the lower areas of an STI region, such as bene... | 03/07/2006 |
| 7005340 | Method for manufacturing semiconductor device A method is provided for manufacturing a semiconductor device that can reduce the number of steps in manufacturing a triple-well that includes multiple ion implantation steps and heat treatment steps. The method comprises the steps of: (a) forming a first mask layer... | 02/28/2006 |
| 7002218 | Low capacitance ESD-protection structure under a bond pad An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection ... | 02/21/2006 |
| 7002222 | Integrated semiconductor memory circuit and method of manufacturing the same An integrated semiconductor circuit, having active components lying in mutually adjoining wells of a respective first and second conduction type, wherein the active components respectively are associated with substrate contacts lying in direct proximity to an edge b... | 02/21/2006 |
| 6989567 | LDMOS transistor A semiconductor transistor structure includes a substrate having an epitaxial layer, a source region extending from the surface of the epitaxial layer, a drain region within the epitaxial layer, a channel located between the drain and source regions, and a gate arra... | 01/24/2006 |
| 6972475 | Semiconductor device A semiconductor device includes an N channel MOS transistor. The N channel MOS transistor includes a first P type buried layer that isolates an N epitaxial region on a P type substrate (P-SUB) from another N epitaxial region, a drain in an N well in the N epitaxial ... | 12/06/2005 |
| 6940110 | SiC-MISFET and method for fabricating the same A storage-type SiC-MISFET includes a SiC substrate, an n-type drift layer, a p-type well region, an n-type source region, a SiC channel layer which contains an n-type impurity and is to be a storage-type channel layer, a p-type heavily doped contact layer, a gate in... | 09/06/2005 |
| 6924177 | Method for producing a thyristor A thyristor having a first zone, a second zone, a third zone, and a fourth zone. At least one control electrode is connected to the second and/or third zone. In order to reduce the static and dynamic power loss in a symmetrical thyristor, it is proposed that a field... | 08/02/2005 |
| 6917095 | Integrated radio frequency circuits A plurality of devices, such as devices that are utilized for implementing radio frequency applications, can be formed in the same substrate. Each of these devices may be formed over a triple well that includes at least one well capable of being biased. Each of the ... | 07/12/2005 |
| 6900518 | Semiconductor device A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals co... | 05/31/2005 |
| 6897536 | ESD protection circuit An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the subs... | 05/24/2005 |
| 6847084 | Semiconductor device A semiconductor device comprises a semiconductor substrate, a first circuit formed on the substrate, and a second circuit connected to the first circuit as an input/output portion thereof and powered by a voltage higher than that for the first circuit, the first cir... | 01/25/2005 |
