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| Number | Title | Issue Date |
| 8084844 | Semiconductor device A semiconductor device in which potential is uniformly controlled and in which the influence of noise is reduced. A p-type well region is formed beneath a surface of a p-type Si substrate. n-type MOS transistors are formed on the p-type well region. An n-type well r... | 12/27/2011 |
| 7944021 | Semiconductor device with suppressed hump characteristic A semiconductor device includes an element isolation film formed on a semiconductor substrate surface of one conductivity type, a gate electrode having one pair of end portions located on a boundary between an element isolation film and an element forming region, a ... | 05/17/2011 |
| 7888775 | Vertical diode using silicon formed by selective epitaxial growth Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertic... | 02/15/2011 |
| 7851889 | MOSFET device including a source with alternating P-type and N-type regions Apparatus and methods are provided for fabricating semiconductor devices with reduced bipolar effects. One apparatus includes a semiconductor body (120) including a surface and a transistor source (300) located in the semiconductor body proximate the s... | 12/14/2010 |
| 7763955 | Reducing shunt currents in a semiconductor body A description is given of a concept for reducing shunt currents in a semiconductor body. ... | 07/27/2010 |
| 7443009 | N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second... | 10/28/2008 |
| 7420260 | Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a f... | 09/02/2008 |
| 7414295 | Transistor and method of operating transistor A transistor in which a physical property of its channel is changed according to an applied voltage, and methods of manufacturing and operating the same are provided. The transistor may include a first conductive layer on a substrate, a phase change layer and a seco... | 08/19/2008 |
| 7411271 | Complementary metal-oxide-semiconductor field effect transistor A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second ... | 08/12/2008 |
| 7402885 | LOCOS on SOI and HOT semiconductor device and method for manufacturing One or more local oxidation of silicon (LOCOS) regions may be formed that apply compressive strain to a channel of a field-effect transistor such as a P-type field-effect transistor (PFET) or other circuit element of a semiconductor device. For instance, a pair of L... | 07/22/2008 |
| 7391095 | Semiconductor device In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in co... | 06/24/2008 |
| 7385275 | Shallow trench isolation method for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel regi... | 06/10/2008 |
| 7361981 | Pad layout A pad layout suitable for being applied on a metal interconnection structure of an integrated circuit chip is provided. The pad layout includes a first signal pad, a second signal pad, a first non-signal pad, a second non-signal pad, a first trace, a second trace, a... | 04/22/2008 |
| 7319263 | Semiconductor component with switching element configured to reduce parasitic current flow A semiconductor component is described. In one embodiment, the semiconductor component includes a switching element integrated in the semiconductor component between two functional element semiconductor regions, configured to reduce a parasitic current flow through ... | 01/15/2008 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7301219 | Electrically erasable programmable read only memory (EEPROM) cell and method for making the same An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to th... | 11/27/2007 |
| 7253487 | Integrated circuit chip having a seal ring, a ground ring and a guard ring An integrated circuit chip is provided. The chip includes a silicon substrate, a circuit, a seal ring, a ground ring and a guard ring. The circuit is formed on the silicon substrate and has an input/output (I/O) pad. The seal ring is formed on the silicon substrate ... | 08/07/2007 |
| 7231325 | System for evaluating a sensor signal The inventive device for evaluating the sensor signal includes the provider for providing the sensor signal, the processor for processing the sensor signal and for providing an information signal comprising information regarding the amplitude course of the sensor si... | 06/12/2007 |
| 7193293 | Semiconductor component with a compensation layer, a depletion zone, and a complementary depletion zone, circuit configuration with the semiconductor component, and method of doping the compensation layer of the semiconductor component A semiconductor component, which functions according to the principle of charge carrier compensation, has incompletely ionized dopants that are additionally provided in a semiconductor body of the semiconductor component. When a reverse voltage is applied, the degre... | 03/20/2007 |
| 7187056 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 03/06/2007 |
| 7145211 | Seal ring for mixed circuitry semiconductor devices In mixed-component, mixed-signal, semiconductor devices, selective seal ring isolation from the substrate and its electrical potential is provided in order to segregate noise sensitive circuitry from electrical noise generated by electrically noisy circuitry. Approp... | 12/05/2006 |
| 7126452 | Wiring structure, and fabrication method of the same An electrical wiring structure, such as a planar coil, includes a set of wiring formed of an electrical conductor and formed on an insulating surface of a substrate. A dam-up wall structure is provided around an outermost peripheral portion of the set of wiring on t... | 10/24/2006 |
| 7110232 | Semiconductor circuit with protective circuit A semiconductor circuit in a semiconductor substrate includes a first input for feeding a first supply potential, a second input for feeding a second supply potential higher than the first supply potential, a device, an output and a parasitic pn-junction between the... | 09/19/2006 |
| 7087496 | Seal ring for integrated circuits The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that... | 08/08/2006 |
| 7087981 | Metal semiconductor contact, semiconductor component, integrated circuit arrangement and method The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive meta... | 08/08/2006 |
| 7064414 | Heater for annealing trapped charge in a semiconductor device A structure and associated method for annealing a trapped charge from a semiconductor device. The semiconductor structure comprises a substrate and a first heating element. The substrate comprises a bulk layer, an insulator layer and a device layer. The first heatin... | 06/20/2006 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer A semiconductor device and a method of fabricating a semiconductor device having multiple subcollectors which are formed in a common wafer, in order to provide multiple structures having different characteristic and frequency response are provided. The subcollectors... | 06/20/2006 |
| 7053453 | Substrate contact and method of forming the same A substrate contact and semiconductor chip, and methods of forming the same. The substrate contact is employable with a semiconductor chip formed from a semiconductor substrate and includes a seal ring region about a periphery of an integrated circuit region. In one... | 05/30/2006 |
| 7029981 | Radiation hardened bipolar junction transistor A method of forming bipolar junction devices, including forming a mask to expose the total surface of the emitter region and adjoining portions of the surface of the base region. A first dielectric layer is formed over the exposed surfaces. A field plate layer is fo... | 04/18/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6995450 | Semiconductor device with a frequency selective guard ring A ring-shaped P+ type diffusion region is formed on the top surface of a P type substrate in such a way as to surround a single internal circuit region. A shunt wiring is formed in an area including directly above the P+ type diffusion region o... | 02/07/2006 |
| 6972475 | Semiconductor device A semiconductor device includes an N channel MOS transistor. The N channel MOS transistor includes a first P type buried layer that isolates an N epitaxial region on a P type substrate (P-SUB) from another N epitaxial region, a drain in an N well in the N epitaxial ... | 12/06/2005 |
| 6972476 | Diode and diode string structure A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped ... | 12/06/2005 |
| 6938224 | Method for modeling noise emitted by digital circuits A method of predicting the electromagnetic noise emitted by a digital circuit on an integrated circuit is disclosed. In accordance with the illustrative embodiment, the output of each digital circuit element in the digital circuit is considered as a bit stream. All ... | 08/30/2005 |
| 6909150 | Mixed signal integrated circuit with improved isolation An integrated circuit having improved isolation includes a first circuit section formed in a substrate and a second circuit section formed in the substrate, the second circuit section being spaced laterally from the first circuit section. The integrated circuit furt... | 06/21/2005 |
| 6906355 | Semiconductor device A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the f... | 06/14/2005 |
| 6900518 | Semiconductor device A power semiconductor device has an active region that includes a drift region. At least a portion of the drift region is provided in a membrane which has opposed top and bottom surfaces. In one embodiment, the top surface of the membrane has electrical terminals co... | 05/31/2005 |
| 6879023 | Seal ring for integrated circuits The present invention is directed to a seal structure and a method for forming a seal structure for a semiconductor die. An elongate region which is electrically isolated from the remainder of the substrate, such as a well region of a conductivity type opposite that... | 04/12/2005 |
| 6800925 | Integrated circuit configuration having a structure for reducing a minority charge carrier current An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and a second semiconductor zone of the first conductivity type adjoining the first semiconductor zone and do... | 10/05/2004 |
| 6756280 | Semiconductor device and a process for producing same In a semiconductor device having a junction type diode using a bipolar transistor and a process for producing the same, a ratio of a diode electric current to a leakage electric current is improved, and latch up resistance is improved without increasing the process.... | 06/29/2004 |
