Class 257/545 - With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the device is provided with means,
No. of patents: 38
Last issue date: 06/28/2011

Number	Title	Issue Date
7968970	Semiconductor device, method for manufacturing semiconductor device, and power amplifier element A semiconductor device is presented, which includes a semiconductor substrate with a high concentration impurity of a first type conductivity and an epitaxial layer with a low concentration impurity provided on the semiconductor substrate, where a trench coupled to ...	06/28/2011
7615845	Active shielding of conductors in MEMS devices An apparatus that reduces parasitic capacitance in a MEMS device includes a dielectric layer on the surface of a silicon-on-insulator (SOI) substrate, a conductor embedded in the substrate and disposed between the dielectric layer and a buried oxide layer, and surfa...	11/10/2009
7411271	Complementary metal-oxide-semiconductor field effect transistor A complementary metal-oxide-semiconductor field effect transistor (CMOSFET) is provided. The CMOSFET includes a substrate of a first conductivity type, a first epitaxial layer, a well, a second epitaxial layer of a second conductivity type, a first sinker, a second ...	08/12/2008
7385275	Shallow trench isolation method for shielding trapped charge in a semiconductor device A semiconductor structure and associated method for forming the semiconductor structure. The semiconductor structure comprises a first field effect transistor (FET), a second FET, and a shallow trench isolation (STI) structure. The first FET comprises a channel regi...	06/10/2008
7345355	Complementary junction-narrowing implants for ultra-shallow junctions Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two spec...	03/18/2008
7335956	Capacitor device with vertically arranged capacitor regions of various kinds A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor de...	02/26/2008
7199407	Semiconductor device An island-shaped floating conducting region is provided in a region of the substrate between the adjacent wires on the nitride film, between the adjacent wire on the nitride film and conducting region (the operating region, resistor, or peripheral impurity region), ...	04/03/2007
7176091	Drain-extended MOS transistors and methods for making the same Drain-extended MOS transistors (T1, T2) and semiconductor devices (102) are described, as well as fabrication methods (202) therefor, in which a p-buried layer (130) is formed prior to formation of epitaxial silicon (106) ov...	02/13/2007
7119393	Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ...	10/10/2006
7067899	Semiconductor integrated circuit device A semiconductor integrated circuit device according to the invention includes an N-type embedded diffusion region between a substrate and a first epitaxial layer in island regions serving as small signal section. The substrate and the first epitaxial layer are thus ...	06/27/2006
6815771	Silicon on insulator device and layout method of the same A silicon on insulator (SOI) semiconductor device includes a wire connected to doped regions formed in an active layer of a SOI substrate. A ratio of the area of the wire to the doped region or a ratio of the area of contact holes formed on the wire to the doped reg...	11/09/2004
6759726	Formation of an isolating wall A method of forming an isolating wall in a semiconductor substrate of a first conductivity type, including the steps of boring in the substrate separate recesses according to the desired isolating wall contour; filling the recesses with a material containing a dopan...	07/06/2004
6664607	Diode having breakdown voltage adjustable to arbitrary value without increase of parasitic capacitance and process for fabrication thereof A lightly doped n-type semiconductor layer is epitaxially grown on a heavily doped n-type semiconductor substrate, and a heavily doped n-type impurity region, a lightly doped p-type deep guard ring and a heavily doped p-type shallow impurity region are fo...	12/16/2003
6501139	High-voltage transistor and fabrication process A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed...	12/31/2002
6469365	Semiconductor component with a structure for avoiding parallel-path currents and method for fabricating a semiconductor component A semiconductor component having a structure for avoiding parallel-path currents in the semiconductor component includes a substrate of a first conductivity type having a surface. A plurality of separate wells of a second conductivity type with a more hig...	10/22/2002
6441456	Semiconductor device and a process for manufacturing the same A semiconductor device comprises:a semiconductor substrate; a plurality of active regions for forming semiconductor elements, the active regions being formed on the semiconductor substrate; a device isolation region for separating the plural active region...	08/27/2002
6433407	Semiconductor integrated circuit A protection circuit in a semiconductor integrated circuit having a master slice I/O circuit comprises an internal circuit, a pad, and a desired number of protection elements connected in parallel between the internal circuit and the pad. Each protection ...	08/13/2002
6420774	Low junction capacitance semiconductor structure and I/O buffer A low junction capacitance semiconductor structure and an I/O buffer are disclosed. The semiconductor structure includes a MOS transistor and a lightly doped region. The MOS transistor is formed in a semiconductor substrate and has a gate and source and d...	07/16/2002
6384455	MOS semiconductor device with shallow trench isolation structure and manufacturing method thereof A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a bur...	05/07/2002
6346736	Trench isolated semiconductor device The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portio...	02/12/2002
6239472	MOSFET structure having improved source/drain junction performance A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in ...	05/29/2001
6002158	High breakdown-voltage diode with electric-field relaxation region A high breakdown-voltage diode is provided, which has a decreased chip area and a low electric resistance between anode and cathode regions after the breakdown phenomenon takes place. A semiconductor layer of a first conductivity type is vertically isolat...	12/14/1999
5932905	Article comprising a capacitor with non-perovskite Sr-Ba-Ti oxide dielectric thin film Ba--Sr--Ti-oxide dielectric material, with at least 60 atomic percent of the total content of the oxide being Ti, can have relatively high dielectric constant K (>40 at 20° C.) and relatively low second order voltage coefficient a2 of the diel...	08/03/1999
5929506	Isolated vertical PNP transistor and methods for making same in a digital BiCMOS process A vertical PNP transistor (11) and method for making it includes forming an N- region (19) in a P substrate (12), and forming an N+ region (26) in the substrate (12) laterally surrounding and partially extending into the N- region (19). A P region (30) is...	07/27/1999
5899714	Fabrication of semiconductor structure having two levels of buried regions Integrated circuits suitable for high-performance applications, especially mixed signal products that have analog and digital sections, are fabricated from a semiconductor structure in which lower buried regions of opposite conductivity types are situated...	05/04/1999
5821601	Bipolar semiconductor integrated circuit with a protection circuit A bipolar semiconductor integrated circuit has a pnp transistor through which a DC power is supplied from an external DC power to various elements of the bipolar IC and a constant current circuit for turning the pnp transistor on and regulating the base c...	10/13/1998
5567978	High voltage, junction isolation semiconductor device having dual conductivity tape buried regions and its process of manufacture A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N ...	10/22/1996
5495124	Semiconductor device with increased breakdown voltage A low concentration impurity region 6 of a second conductivity type is formed to cover lower portion of a high concentration impurity region 8 of the second conductivity type. Consequently, impurity concentration gradient between the high concentration im...	02/27/1996
5455447	Vertical PNP transistor in merged bipolar/CMOS technology A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried l...	10/03/1995
5434444	High breakdown voltage semiconductor device A high breakdown voltage semiconductor device comprising a semiconductor substrate an insulating layer formed on the semiconductor substrate, a high resistance semiconductor layer formed on the insulating layer, an isolation region formed in the high resi...	07/18/1995
5382820	High voltage CMOS device to integrate low voltage controlling device A method of fabrication of an semiconductor device comprises applying an impurity of a predetermined polarity to a silicon substrate; forming a well by applying an impurity of an opposite polarity to a region in the silicon substrate; forming a first mask...	01/17/1995
5300805	Epitaxial tub bias structure for integrated circuits A bias structure for an integrated circuit including first and second transistors having emitter terminals coupled respectively to the supply and to a terminal of a resistor whose potential, under certain operating conditions of the circuit, exceeds the s...	04/05/1994
5241210	High breakdown voltage semiconductor device A high breakdown voltage semiconductor device includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first semiconductor region formed on the first insulating film, a second semiconductor region of a first con...	08/31/1993
5124761	Semiconductor apparatus A semiconductor apparatus of the present invention comprises, as, for example, shown in FIG. 5, a semiconductor region (32) of first conductivity type formed on a semiconductor substrate (31), and a semiconductor region (34) of second conductivity type fo...	06/23/1992
4969030	Integrated structure for a signal transfer network, in particular for a pilot circuit for MOS power transistors The integrated structure is formed of various circuital components accomplished by diffusion of dopants in a semiconductor substrate. Each component is located inside a respective insulation recess electrically floating in relation to the substrate and th...	11/06/1990
4935796	Device for minimizing parasitic junction capacitances in an insulated collector vertical P-N-P transistor A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its...	06/19/1990
4839735	Solid state image sensor having variable charge accumulation time period A solid state image sensor in which the charge accumulation period of each picture element can be set at the same point of time. Additionally, the lenngth of the charge period can be set at will, thus providing a video signal picture in which all picture ...	06/13/1989
4794443	Semiconductor device and process for producing same A semiconductor device, e.g. a photoelectric converter, comprises a semiconductor transistor having a semiconductor controlling electrode region of one conductivity type resettable at a desired stage, an element isolation region of the same conductivity t...	12/27/1988

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Class 257/545 - With means to control isolation junction capacitance (e.g., lightly doped layer at isolation junction to increase depletion layer width)