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| Number | Title | Issue Date |
| 8129817 | Reducing high-frequency signal loss in substrates An integrated circuit structure includes a semiconductor substrate of a first conductivity type; and a depletion region in the semiconductor substrate. A deep well region is substantially enclosed by the depletion region, wherein the deep well region is of a second ... | 03/06/2012 |
| 8084843 | N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second... | 12/27/2011 |
| 7868422 | MOS device with a high voltage isolation structure The present invention discloses a semiconductor structure. A buried layer of a first polarity type is constructed on a semiconductor substrate. A first epitaxial layer of a second polarity type is formed on the buried layer. A second epitaxial layer of the second po... | 01/11/2011 |
| 7834421 | Isolated diode Various integrated circuit devices, in particular a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielec... | 11/16/2010 |
| 7825492 | Isolated vertical power device structure with both N-doped and P-doped trenches A method for manufacturing an isolated vertical power device includes forming, in a back surface of a first conductivity type substrate, back isolation wall trenches that surround a conduction region of the device. In a front surface of the substrate, front isolatio... | 11/02/2010 |
| 7808078 | Semiconductor device and manufacturing method thereof A semiconductor integrated circuit is reduced in size by suppressing lateral extension of an impurity region when impurities in the impurity region are thermally diffused in a semiconductor substrate. A second photoresist is formed on an insulation film. The second ... | 10/05/2010 |
| 7795702 | Microelectronic assemblies with improved isolation voltage performance Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below ... | 09/14/2010 |
| 7768100 | Semiconductor integrated circuit This invention is directed to improve the electrostatic discharge strength and the latch-up strength of the semiconductor integrated circuit. To achieve the certain level of stable quality of the semiconductor integrated circuit by eliminating the variety in the ele... | 08/03/2010 |
| 7675140 | Semiconductor circuit device and display data line driver An N-type diffusion layer fixed at a potential equal to or above 0V is provided in a segregating region between terminals, and a P-type diffusion layer having a potential equal to that of the N-type diffusion layer on an N-type well constitute a drain of a transisto... | 03/09/2010 |
| 7443009 | N well implants to separate blocks in a flash memory device A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second... | 10/28/2008 |
| 7419868 | Gated diode nonvolatile memory process A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the indiv... | 09/02/2008 |
| 7404247 | Method for making a pressure sensor A method for making a pressure sensor including the steps of providing a substrate and forming or locating a pressure sensing component on the substrate. The method further includes the step of, after the forming or locating step, etching a cavity in the substrate b... | 07/29/2008 |
| 7394143 | Semiconductor integrated circuit device Repeaters are arranged at arbitrary positions to substantially improve transmission speed of a signal. In the semiconductor integrated circuit device 1, repeater regions 10 where repeaters are provided as relay points for wiring are provided in the cen... | 07/01/2008 |
| 7391045 | Three-dimensional phase-change memory A three-dimensional phase-change memory array. In one embodiment of the invention, the memory array includes a first plurality of diodes, a second plurality of diodes disposed above the first plurality of diodes, a first plurality phase-change memory elements dispos... | 06/24/2008 |
| 7368337 | Semiconductor device and manufacturing method thereof A semiconductor device and method of manufacturing the same are disclosed. An example semiconductor device includes a semiconductor substrate having a first well, a first source electrode, a drain electrode, and a first gate insulation layer formed on the semiconduc... | 05/06/2008 |
| 7348657 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 03/25/2008 |
| 7323763 | Semiconductor device having an improved voltage controlled oscillator A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The var... | 01/29/2008 |
| 7310259 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 12/18/2007 |
| 7276772 | Semiconductor device A semiconductor device, including: a semiconductor substrate of a first conduction type; an active region used as a function-element-forming region on the semiconductor substrate; a low-resistance region of a second conduction type formed on an outermost periphery o... | 10/02/2007 |
| 7276769 | Semiconductor integrated circuit device In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor ele... | 10/02/2007 |
| 7259426 | Semiconductor device and its manufacturing method There is provided a power MISFET which includes a semiconductor region of a first conductivity, a semiconductor base region of a second conductivity, a pillar region, a first major electrode region of a first conductivity on the base region, a second major electrode... | 08/21/2007 |
| 7235445 | Methods of forming device with recessed gate electrodes Methods are provided for forming a device, such as a semiconductor device. A field region and an active region of a substrate are defined in which the field region has an upper surface that extends further away from the substrate and is higher than an upper surface ... | 06/26/2007 |
| 7205628 | Semiconductor device A semiconductor device, including: a semiconductor substrate of a first conduction type; an active region used as a function-element-forming region on the semiconductor substrate; a low-resistance region of a second conduction type formed on an outermost periphery o... | 04/17/2007 |
| 7196373 | NAND flash memory device and method of forming a well of a NAND flash memory device Disclosed herein are a NAND flash memory device and a method of forming a well of the NAND flash memory device. Triple wells of a NAND flash memory device are formed within a cell region in plural. A cell block including flash memory cells is formed on the triple we... | 03/27/2007 |
| 7196392 | Semiconductor structure for isolating integrated circuits of various operation voltages A semiconductor structure includes an isolation ring disposed on a semiconductor substrate, surrounding first and second circuit areas. A buried isolation layer is continuously extended through the first circuit area and the second circuit area, in the semiconductor... | 03/27/2007 |
| 7193292 | Fuse structure with charge protection circuit A fuse structure for memory cell repair in a RAM device. The fuse structure includes a substrate, a fuse layer over an isolation region on the substrate, a charge protection circuit electrically connected to one side of the fuse layer, and two conductive layers over... | 03/20/2007 |
| 7187058 | Semiconductor component having a pn junction and a passivation layer applied on a surface The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101 | 03/06/2007 |
| 7173315 | Semiconductor device In a semiconductor device in which a control circuit region and a power transistor region are formed, a first dummy region is formed between a ground side transistor composing a push-pull circuit and the control circuit region while a second dummy region is formed b... | 02/06/2007 |
| 7148551 | Semiconductor energy detector A semiconductor energy detector includes a semiconductor substrate comprised of a semiconductor of a first conductivity type, into which an energy ray of a predetermined wavelength range is incident from an incident surface thereof. A semiconductor energy detector i... | 12/12/2006 |
| 7138700 | Semiconductor device with guard ring for preventing water from entering circuit region from outside A semiconductor device has a first guard ring surrounding a circuit region, a second ring disposed between the circuit region and the first guard ring, and first connections connecting the first guard ring and the second guard ring to each other. An area sandwiched ... | 11/21/2006 |
| 7138686 | Integrated circuit with improved signal noise isolation and method for improving signal noise isolation A system-on chip (SOC) (100) and method of isolating noise in a SOC, including a plurality of noise sensitive circuit blocks (120, 220) and ESD protected pads (302, 304, 306, 308, 310, 312, and 314). A VDD isolation pad (302) is co... | 11/21/2006 |
| 7138701 | Electrostatic discharge protection networks for triple well semiconductor devices An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. ... | 11/21/2006 |
| 7135755 | Integrated semiconductor device providing for preventing the action of parasitic transistors An electric motor drive system is disclosed which includes a required number of motor driver circuits connected one to each motor armature coil. Fabricated in the form of an integrated circuit, each such motor driver circuit has a parasitic transistor unavoidably cr... | 11/14/2006 |
| 7135718 | Diode device and transistor device A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the ... | 11/14/2006 |
| 7116570 | Access circuit and method for allowing external test voltage to be applied to isolated wells An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective well... | 10/03/2006 |
| 7098512 | Layout patterns for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface ... | 08/29/2006 |
| 7078782 | Semiconductor device To attain reduction in size of a semiconductor device having a power transistor and an SBD, a semiconductor device according to the present invention comprises a first region and a second region formed on a main surface of a semiconductor substrate; plural first con... | 07/18/2006 |
| 7026704 | Semiconductor device for reducing plasma charging damage A semiconductor device and method of manufacturing the semiconductor device including a semiconductor substrate of a first conductivity type. A scribe lane area formed in the substrate to define chip formation areas. A deep well area formed in each chip formation ar... | 04/11/2006 |
| 7022574 | Multi-voltage level semiconductor device and its manufacture In a semiconductor device comprising a MOS transistor driven at a relatively low voltage and a MOS transistor driven at a relatively high voltage formed on the same semiconductor substrate, the MOS transistor driven at the relatively high voltage comprises: a first ... | 04/04/2006 |
| 6972466 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 12/06/2005 |
