Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8138573 | On-chip heater and methods for fabrication thereof and use thereof An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substra... | 03/20/2012 |
| 8076754 | Silicide-interface polysilicon resistor A silicide-interface polysilicon resistor is disclosed. The silicide-interface polysilicon resistor includes a substrate, an oxide layer located on top of the substrate, and a polysilicon layer located on top of the oxide layer. The polysilicon layer includes multip... | 12/13/2011 |
| 8030738 | Semiconductor device with resistor pattern and method of fabricating the same Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a ... | 10/04/2011 |
| 7939911 | Back-end-of-line resistive semiconductor structures In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewa... | 05/10/2011 |
| 7795701 | Semiconductor device and manufacturing method thereof A first insulation film is provided on a semiconductor substrate. A high resistance element formed from polysilicon is provided on the first insulation film. A second insulation film is provided on the high resistance element. A hydrogen diffusion preventing film ha... | 09/14/2010 |
| 7566946 | Precision passive circuit structure A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive... | 07/28/2009 |
| 7518214 | Semiconductor device and method of fabricating the same An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of... | 04/14/2009 |
| 7514762 | Active matrix pixel device with photo sensor An active matrix pixel device including a plurality of polycrystalline silicon islands supported by a substrate, one of the polycrystalline silicon islands providing a channel and doped source/drain regions of a thin film transistor, a PIN diode which includes a p-t... | 04/07/2009 |
| 7443008 | Lateral programmable polysilicon structure incorporating polysilicon blocking diode A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable s... | 10/28/2008 |
| 7427802 | Irreversible reduction of the value of a polycrystalline silicon resistor The invention relates to a method and device for the irreversible reduction of the value of an integrated polycrystalline silicon resistor. The inventive method consists in temporarily subjecting the resistor to a stress current which is greater than a current (Im) ... | 09/23/2008 |
| 7405464 | Array substrate, method of manufacturing the same and method of crystallizing silicon An array substrate includes a base substrate, a switching element, and a pixel electrode. The switching element is on the base substrate. The switching element includes a poly silicon pattern having at least one block. Grains are formed in each of the at least one b... | 07/29/2008 |
| 7365397 | Semiconductor device The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b | 04/29/2008 |
| 7354805 | Method of making electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 04/08/2008 |
| 7352050 | Fuse region of a semiconductor region In a fuse region of a semiconductor device, and a method of fabricating the same, the fuse region includes an interlayer insulating layer on a semiconductor substrate, a plurality of fuses on the interlayer insulating layer disposed in parallel with each other, a bl... | 04/01/2008 |
| 7351639 | Increasing an electrical resistance of a resistor by oxidation or nitridization A method and structure for increasing an electrical resistance of a resistor that is within a semiconductor structure, by oxidizing or nitridizing a fraction of a surface layer of the resistor with oxygen/nitrogen (i.e., oxygen or nitrogen) particles, respectively. ... | 04/01/2008 |
| 7335967 | Semiconductor device A semiconductor device is provided that includes: a base insulating film; a metal thin-film resistor that is provided on the base insulating film; a lower-layer insulating film that is formed under the base insulating film; and a wiring pattern that is formed on the... | 02/26/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7317239 | Method for manufacturing a resistor A method of manufacturing a resistor is provided. At first, a semiconductor layer including at least a high resistance region and a low resistance region is formed on a substrate. Following that, a first ion implantation process is performed to the entire surface of... | 01/08/2008 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 12/11/2007 |
| 7304366 | Self correcting multiple-link fuse An improved fuse link structure and fuse blowing method, the fuse-link structure including a plurality of elongated fuse-link members comprising polysilicon electrically connected in parallel according to a common input Voltage contact and common output current cont... | 12/04/2007 |
| 7300807 | Structure and method for providing precision passive elements A circuit having a precision passive circuit element, such as a resistor or a capacitor, with a target value of an electrical parameter is fabricated on a substrate with a plurality of independent parallel-connected passive circuit elements. The plurality of passive... | 11/27/2007 |
| 7285472 | Low tolerance polysilicon resistor for low temperature silicide processing Various methods of fabricating a high precision, silicon-containing resistor in which the resistor is formed as a discrete device integrated in complementary metal oxide semiconductor (CMOS) processing utilizing low temperature silicidation are provided. In some emb... | 10/23/2007 |
| 7262136 | Modified facet etch to prevent blown gate oxide and increase etch chamber life A modified facet etch is disclosed to prevent blown gate oxide and increase etch chamber life. The modified facet etch is a two-stage process. The first stage is a plasma sputter etch to form a facet profile. The first stage etch is terminated prior to reaching the ... | 08/28/2007 |
| 7262476 | Semiconductor device having improved power density An MOS device is formed including a semiconductor layer of a first conductivity type, and source and drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The source and drain regions are... | 08/28/2007 |
| 7256456 | SOI substrate and semiconductor integrated circuit device A semiconductor IC device includes a base substrate comprising P−-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provide... | 08/14/2007 |
| 7242074 | Reduced capacitance resistors A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-s... | 07/10/2007 |
| 7242072 | Electrically programmable fuse for silicon-on-insulator (SOI) technology A fuse structure and method of forming the same is described, wherein the body of the fuse is formed from a crystalline semiconductor body on an insulator, preferably of a silicon-on-insulator wafer, surrounded by a fill-in dielectric. The fill-in dielectric is pref... | 07/10/2007 |
| 7239006 | Resistor tuning A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact region... | 07/03/2007 |
| 7227380 | Synchronous first-in/first-out block memory for a field programmable gate array The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plur... | 06/05/2007 |
| 7223668 | Method of etching metallic thin film on thin film resistor An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and ope... | 05/29/2007 |
| 7214613 | Cross diffusion barrier layer in polysilicon A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of sec... | 05/08/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7199016 | Integrated circuit resistor An integrated circuit resistor is provided that comprises a mesa 14 between electrical contacts 16 and 18. The electrical resistance between electrical contacts 16 and 18 is selectively increased through the formation of recesses | 04/03/2007 |
| 7176504 | SiGe MOSFET with an erosion preventing SiGelayer A semiconductor device is provided. The semiconductor device comprises a substrate, a gate structure, a spacer, a SixGey layer and a SixGey protection layer. The gate structure is deposited on the substrate and the spacer ... | 02/13/2007 |
| 7176553 | Integrated resistive elements with silicidation protection In a process for the fabrication of integrated resistive elements with protection from silicidation, at least one active area (15) is delimited in a semiconductor wafer (10). At least one resistive region (21) having a pre-determined resistivity... | 02/13/2007 |
| 7176485 | Damascene resistor and method for measuring the width of same A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped regio... | 02/13/2007 |
| 7169661 | Process of fabricating high resistance CMOS resistor A process of forming a high resistance CMOS resistor with a relatively small die size is provided. According to an aspect of the present invention, the process of fabricating a high resistance resistor is a standard CMOS process that does not require any additional ... | 01/30/2007 |
| 7166896 | Cross diffusion barrier layer in polysilicon A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of sec... | 01/23/2007 |
| 7161229 | Minimizing end boundary resistance in a programmable resistor of an integrated circuit A programmable resistor includes a variety of taps. Selection of any of a variety of tap combinations establishes a path through which current will flow, thus, setting the resistance value of the programmable resistor. The programmable resistor minimizes the effects... | 01/09/2007 |
| 7145255 | Lateral programmable polysilicon structure incorporating polysilicon blocking diode A programmable element includes a diode and a programmable structure formed in a polysilicon layer isolated from a semiconductor substrate by a dielectric layer. The diode includes a first region and a second region of opposite conductivity types. The programmable s... | 12/05/2006 |
