Famous Patents
The first match was accidentally discovered in 1826 when John Walker scraped a stick with chemicals on the end against a stone floor.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7342293 | Bipolar junction transistors (BJTS) with second shallow trench isolation (STI) regions, and methods for forming same The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends betwe... | 03/11/2008 |
| 7335910 | Thin film transistor, semiconductor device, display, crystallization method, and method of manufacturing thin film transistor An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and ... | 02/26/2008 |
| 7285473 | Method for fabricating low-defect-density changed orientation Si The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystal... | 10/23/2007 |
| 7208815 | CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substra... | 04/24/2007 |
| 7208803 | Method of forming a raised source/drain and a semiconductor device employing the same A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a direc... | 04/24/2007 |
| 7196400 | Semiconductor device with enhanced orientation ratio and method of manufacturing same An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a cryst... | 03/27/2007 |
| 7183598 | Colors only process to reduce package yield loss Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmit... | 02/27/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7138319 | Deep trench isolation of embedded DRAM for improved latch-up immunity A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic... | 11/21/2006 |
| 7102166 | Hybrid orientation field effect transistors (FETs) A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c)... | 09/05/2006 |
| 7094634 | Structure and method for manufacturing planar SOI substrate with multiple orientations The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface co... | 08/22/2006 |
| 7084483 | Trench type buried on-chip precision programmable resistor An on-chip, ultra-compact, and programmable semiconductor resistor device and device structure and a method of fabrication. Each semiconductor resistor device structure is formed of one or more conductively connected buried trench type resistor elements exhibiting a... | 08/01/2006 |
| 7045880 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim... | 05/16/2006 |
| 7023057 | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive or insulating interface is provided. Also provid... | 04/04/2006 |
| 6995456 | High-performance CMOS SOI devices on hybrid crystal-oriented substrates Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. The first-type transistors are on first portions of the substrate that have a first type of crystalline orientation and second-type transistors a... | 02/07/2006 |
| 6960821 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim... | 11/01/2005 |
| 6903368 | Thin-film transistor device, its manufacturing process, and image display using the device A thin film made of silicon or another IV-group crystals (crystals and mixed crystals of C, Ge, Sn, and Pb) is twice scanned with a laser beam moving in two lateral directions in which crystal grains grow larger in order to form high-quality polycrystals in exact po... | 06/07/2005 |
| 6825115 | Post silicide laser thermal annealing to avoid dopant deactivation Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/dra... | 11/30/2004 |
| 6730981 | Bipolar transistor with inclined epitaxial layer In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer at the surface of the N− epitaxial layer is inclined upwar... | 05/04/2004 |
| 6639280 | Semiconductor device and semiconductor chip using SOI substrate A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis... | 10/28/2003 |
| 6486525 | Deep trench isolation for reducing soft errors in integrated circuits An integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit are disclosed. The integrated circuit comprises a substrate 72, a transistor formed in the substrate 72, a first region 7... | 11/26/2002 |
| 6404027 | High dielectric constant gate oxides for silicon-based devices A high dielectric rare earth oxide of the form Mn2 O3 (such as, for example, Gd2 O3 or Y2 O3) is grown on a clean silicon (100) substrate surface under an oxygen partial pressure less than ... | 06/11/2002 |
| 6198149 | Semiconductor device having novel insulating film structure A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a g... | 03/06/2001 |
| 6040597 | Isolation boundaries in flash memory cores A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of ... | 03/21/2000 |
| 5962892 | MISFET and complementary MISFET device having high performance source and drain diffusion layer A source and drain diffusion layer of a transistor has a junction of a shallow depth and low in parasitic resistance and parasitic capacitance. The transistor includes a gate insulator formed on a principal plane of a semiconductor substrate, a gate electrode ... | 10/05/1999 |
| 5591665 | Process for producing a semiconductor structure including a plurality of vertical semiconductor devices and at least one lateral semiconductor device integrated in a semiconductor body A method is provided for forming a semiconductor device including a semiconductor body having a first surface and a second surface located opposite the first surface, with a plurality of vertical semiconductor components extending between the first and se... | 01/07/1997 |
| 5296731 | Semiconductor integrated circuit device with alpha rays resistance A semiconductor integrated circuit device according to the present invention includes a semiconductor layer of a first conductivity type having a high concentration of impurity atoms which layer is formed in or on predetermined locations of a semiconducto... | 03/22/1994 |
| 4581814 | Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation The efficacy of dielectrically isolated device formation on a substrate is substantially enhanced through a specific set of processing steps. In particular, before silicon oxide regions, e.g., gate oxide regions, are produced, bulk polycrystalline areas a... | 04/15/1986 |
| 4131910 | High voltage semiconductor devices Disclosed are dielectrically isolated high voltage planar devices and methods of fabricating such devices. The devices are designed so that the large electric fields at the junction edges are significantly reduced; thereby permitting a closely packed stru... | 12/26/1978 |
| 4106050 | Integrated circuit structure with fully enclosed air isolation An integrated circuit member structure comprising a semiconductor substrate having formed therein a pattern of cavities extending from one surface of the substrate into the substrate and fully enclosed within said member, a plurality of pockets of semicon... | 08/08/1978 |
| 4063271 | FET and bipolar device and circuit process with maximum junction control Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and... | 12/13/1977 |
| 4042949 | Semiconductor devices Various devices are described herein utilizing anisotropic etching and dielectric isolations as means for limiting areas of either conductivity type semiconductor material. Surface junctions normally found in the diffused semiconductor devices of the prio... | 08/16/1977 |
| 3969749 | Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide Process permitting control of the thickness of the thin layer of semiconductor material by first forming a slot of a predetermined depth in one surface so that the slot will be exposed during removal of material from the opposite surface should the thickn... | 07/13/1976 |
