Did You Know...
...that several people are credited with the invention of the flush toilet? Most people have heard of Thomas Crapper (1837-1910), the sanitary engineer who invented the valve-and-siphon arrangement that made the modern toilet possible. Another claimant to "the throne" was British inventor Alexander Cumming who patented a toilet in 1775. Then there's a nameless Minoan (a native of ancient Crete) who lived 4,000 years ago who supposedly was ahead of his time and created the first flush toilet!
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| Number | Title | Issue Date |
| 7919829 | Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content ... | 04/05/2011 |
| 7435661 | Polish stop and sealing layer for manufacture of semiconductor devices with deep trench isolation A method and resulting device that eliminates vertical steps or gaps in a deep trench isolation region and, thus, eliminates or drastically reduces a possibility of polysilicon stringers. Additionally, the invention allows an inexpensive dielectric material, for exa... | 10/14/2008 |
| 7420202 | Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and... | 09/02/2008 |
| 7382015 | Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol... | 06/03/2008 |
| 7371658 | Trench isolation structure and a method of manufacture therefor The present invention provides a trench isolation structure, a method of manufacture therefor and a method for manufacturing an integrated circuit including the same. The trench isolation structure (130), in one embodiment, includes a trench located within a ... | 05/13/2008 |
| 7355262 | Diffusion topography engineering for high performance CMOS fabrication Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on t... | 04/08/2008 |
| 7332384 | Technique for forming a substrate having crystalline semiconductor regions of different characteristics Different types of crystalline semiconductor regions are provided on a single substrate by forming a dielectric region within a first crystalline semiconductor region. Thereafter, a second crystalline region is positioned above the dielectric region by wafer bond te... | 02/19/2008 |
| 7326586 | Method for manufacturing semiconductor physical quantity sensor A method for manufacturing a semiconductor physical quantity sensor is provided. The sensor includes a multi-layered substrate, a cavity, a groove, a movable portion and a fixed portion. The multi-layered substrate includes a support substrate, an embedded insulatio... | 02/05/2008 |
| 7312511 | Semiconductor device with electrically isolated ground structures This invention provides a high frequency power module which is incorporated into a mobile phone and which incorporates high frequency portion analogue signal processing ICs including low noise amplifiers which amplify an extremely weak signal therein. A semiconducto... | 12/25/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7279769 | Semiconductor device and manufacturing method thereof To suppress occurrence of dislocation in a substrate of a semiconductor device at an end portion of a gate electrode. Provided is a semiconductor device having a plurality of element formation regions formed over the main surface of a semiconductor substrate, an ele... | 10/09/2007 |
| 7271464 | Liner for shallow trench isolation A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content ... | 09/18/2007 |
| 7268646 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 09/11/2007 |
| 7262486 | SOI substrate and method for manufacturing the same The SOI substrate 1 has a supporting substrate 10, an insulating layer 20 formed on the supporting substrate 10 and a silicon layer 30 formed on the insulating layer 20. A through electrode 40 is provided in a device ... | 08/28/2007 |
| 7258012 | Integrated monolithic tri-axial micromachined accelerometer A monolithic integrated 3-axis accelerometer chip includes a single crystal substrate, the substrate including at least one single crystal membrane layer portion. A single sensor microstructure made from the single crystal membrane senses acceleration in each of the... | 08/21/2007 |
| 7247569 | Ultra-thin Si MOSFET device structure and method of manufacture The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a ... | 07/24/2007 |
| 7235857 | Power semiconductor device A semiconductor device is provided in which a plurality of MOSFETs including a vertical MOSFET is formed on a substrate. The device includes a silicon carbide substrate having front and back surfaces facing each other, an isolating region formed in the substrate to ... | 06/26/2007 |
| 7224038 | Semiconductor device having element isolation trench and method of fabricating the same A semiconductor device capable of preventing defective embedding of an insulator and improving the withstand voltage (dielectric strength) of an element isolation region is obtained. This semiconductor device comprises a semiconductor substrate having a main surface... | 05/29/2007 |
| 7199020 | Nitridation of STI liner oxide for modulating inverse width effects in semiconductor devices A method (1300) of forming a semiconductor device comprising an isolation structure is disclosed, and includes forming a trench region within a semiconductor body (1308). Then, surfaces of the trench region are nitrided (1310) via a nitridation ... | 04/03/2007 |
| 7192887 | Semiconductor device with nitrogen in oxide film on semiconductor substrate and method of manufacturing the same A method of manufacturing a MOS transistor is provided that achieves high-speed devices by reducing nitrogen diffusion to a silicon substrate interface due to redistribution of nitrogen and further suppressing its diffusion to a polysilicon interface, which prevents... | 03/20/2007 |
| 7183615 | Nonvolatile semiconductor memory and manufacturing method for the same A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row a... | 02/27/2007 |
| 7170109 | Heterojunction semiconductor device with element isolation structure A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are lam... | 01/30/2007 |
| 7170146 | TFT structure and method for manufacturing the same A thin film transistor (TFT) structure includes a substrate, a polysilicon structure including a plurality of channel regions, at least one lightly doped region and at least one heavily doped source/drain region, a plurality of gate structures, and an insulating lay... | 01/30/2007 |
| 7164183 | Semiconductor substrate, semiconductor device, and method of manufacturing the same A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress t... | 01/16/2007 |
| 7138319 | Deep trench isolation of embedded DRAM for improved latch-up immunity A protective structure for blocking the propagation of defects generated in a semiconductor device is disclosed. In an exemplary embodiment, the structure includes a deep trench isolation formed between a memory storage region of the semiconductor device and a logic... | 11/21/2006 |
| 7132349 | Methods of forming integrated circuits structures including epitaxial silicon layers in active regions An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active reg... | 11/07/2006 |
| 7122876 | Isolation-region configuration for integrated-circuit transistor A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped wel... | 10/17/2006 |
| 7112866 | Method to form a cross network of air gaps within IMD layer The invention provides a new multilevel interconnect structure of air gaps in a layer of IMD. A first layer of dielectric is provided over a surface; the surface contains metal points of contact. Trenches are provided in this first layer of dielectric. The trenches ... | 09/26/2006 |
| 7112850 | Non-volatile memory device with a polarizable layer This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a s... | 09/26/2006 |
| 7083997 | Bonded wafer optical MEMS process A microelectromechanical system is fabricated from a substrate having a handle layer, a silicon sacrificial layer and a device layer. A micromechanical structure is etched in the device layer and the underlying silicon sacrificial layer is etched away to release the... | 08/01/2006 |
| 7068125 | Temperature controlled MEMS resonator and method for controlling resonator frequency There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a temperature compensated microelectromechanical resonator as well as fabricating, manufacturing, providing and/or controlling microelectromechanical reso... | 06/27/2006 |
| 7023065 | Capacitive resonators and methods of fabrication A micro-electro-mechanical system (MEMS) capacitive resonator and methods for manufacturing the same are invented and disclosed. In one embodiment, a method comprises forming trenches in a substrate, conformally coating the substrate with an oxide, filling the coate... | 04/04/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7015549 | Integrated circuit structures including epitaxial silicon layers that extend from an active region through an insulation layer to a substrate An integrated circuit structure can include an isolation structure that electrically isolates an active region of an integrated circuit substrate from adjacent active regions and an insulation layer that extends from the isolation structure to beneath the active reg... | 03/21/2006 |
| 7009209 | Silicon carbide and related wide-bandgap transistors on semi-insulating epitaxy for high-speed, high-power applications A silicon carbide semi-insulating epitaxy layer is used to create power devices and integrated circuits having significant performance advantages over conventional devices. A silicon carbide semi-insulating layer is formed on a substrate, such as a conducting substr... | 03/07/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6998324 | Methods of fabricating silicon on insulator substrates for use in semiconductor devices Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trench... | 02/14/2006 |
| 6974757 | Method of forming silicon-on-insulator comprising integrated circuitry A wafer bonding method of forming silicon-on-insulator comprising integrated circuitry includes nitridizing at least a portion of an outer surface of silicon of a device wafer. After the nitridizing, the device wafer is joined with a handle wafer. A method of formin... | 12/13/2005 |
| 6964907 | Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ... | 11/15/2005 |
| 6949007 | System and method for multi-stage process control in film removal A fabricating system. A processing tool executes a film removal process on a wafer using a chemical mechanism. A metrology tool monitors surface characteristics of the wafer to obtain a measured film thickness thereof before and after a first removal process, wherei... | 09/27/2005 |
