Class 257/521 - Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the device has grooves for the isolation
No. of patents: 67
Last issue date: 03/15/2011

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Number	Title	Issue Date
7906830	Epitaxial silicon growth Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the...	03/15/2011
7397105	Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted ...	07/08/2008
7382015	Semiconductor device including an element isolation portion having a recess A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isol...	06/03/2008
7335910	Thin film transistor, semiconductor device, display, crystallization method, and method of manufacturing thin film transistor An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and ...	02/26/2008
7214324	Technique for manufacturing micro-electro mechanical structures A technique for manufacturing a micro-electro mechanical structure includes a number of steps. Initially, a cavity is formed into a first side of a handling wafer, with a sidewall of the cavity forming a first angle greater than about 54.7 degrees with respect to a ...	05/08/2007
7208803	Method of forming a raised source/drain and a semiconductor device employing the same A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a direc...	04/24/2007
7198981	Vacuum sealed surface acoustic wave pressure sensor A vacuum sealed SAW pressure sensor is disclosed herein, which includes a sensing element configured as a SAW device (e.g., SAW resonator or SAW delay line) supported by a thin diaphragm. The substrate material can be implemented as a quartz wafer (i.e., a “base�...	04/03/2007
7196400	Semiconductor device with enhanced orientation ratio and method of manufacturing same An object is to enhance the orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film while using as a substrate a less-heat-resistive material such as glass thereby providing a semiconductor device using a cryst...	03/27/2007
7183585	Semiconductor device and a method for the manufacture thereof To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100. ...	02/27/2007
7126187	Semiconductor device and a method of producing the same A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate exte...	10/24/2006
7071513	Layout optimization of integrated trench VDMOS arrays An economical integration of trench VDMOS devices into a conventional BCD process is provided, with the optimization of key aspects of the device layout for low Rds(on) area. Specifically, trench orientation, array geometry, the number of source cells bet...	07/04/2006
7067879	Integration of trench power transistors into a 1.5 μm BCD process The formation of vertical trench DMOS devices can be added to existing integrated BCD process flows in order to improve the efficiency of the BCD devices. The formation of this trench DMOS varies from existing approaches used with discrete trench DMOS devices, in th...	06/27/2006
7045880	Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim...	05/16/2006
6992367	Process for forming a buried cavity in a semiconductor material wafer and a buried cavity The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the f...	01/31/2006
6964907	Method of etching a lateral trench under an extrinsic base and improved bipolar transistor In a BJT, the extrinsic base to collector capacitance is reduced by forming a lateral trench between the extrinsic base region and collector. This is typically done by using an anisotropic wet etch process in a direction of a orientation wafer. ...	11/15/2005
6960821	Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the direction. Advantageously, improvements in hole carrier mobility of approxim...	11/01/2005
6930360	Semiconductor device and manufacturing method of the same A semiconductor device having a semiconductor layer, includes: a first impurity atom having a covalent bond radius larger than a minimum radius of a covalent bond of a semiconductor constituent atom of a semiconductor layer; and a second impurity atom having a coval...	08/16/2005
6903368	Thin-film transistor device, its manufacturing process, and image display using the device A thin film made of silicon or another IV-group crystals (crystals and mixed crystals of C, Ge, Sn, and Pb) is twice scanned with a laser beam moving in two lateral directions in which crystal grains grow larger in order to form high-quality polycrystals in exact po...	06/07/2005
6897095	Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first ...	05/24/2005
6882026	Semiconductor apparatus and process for producing the same, and process for making via hole In a semiconductor apparatus, a plurality of HBTs (heterojunction bipolar transistors) are formed on a front surface consisting of a (100) crystal plane of a GaAs substrate. Via holes passing thorough the GaAs substrate are formed in proximity of the HBTs. Each via ...	04/19/2005
6864534	Semiconductor wafer To provide a semiconductor wafer having crystal orientations of a wafer for the support substrate and a wafer for the device formation shifted from each other, wherein two kinds of wafers having different crystal orientations in which a notch or an orientation flat ...	03/08/2005
6836001	Semiconductor device having epitaxially-filled trench and method for manufacturing semiconductor device having epitaxially-filled trench A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining th...	12/28/2004
6798038	Manufacturing method of semiconductor device with filling insulating film into trench Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench clo...	09/28/2004
6787877	Method for filling structural gaps and integrated circuitry A semiconductor processing method for filling structural gaps includes depositing a substantially boron free silicon oxide comprising material at a first average deposition rate over an exposed semiconductive material in a gap between wordline constructions and at a...	09/07/2004
6750516	Systems and methods for electrically isolating portions of wafers Systems for electrically isolating portions of wafers are provided. A representative system includes a first wafer and a first conductor formed at least partially through the first wafer. A first conductor insulating layer is formed at least partially through the fi...	06/15/2004
6686642	Multi-level integrated circuit for wide-gap substrate bonding An integrated circuit includes a substrate having an etched surface and a non-etched surface. The etched surface contains circuit elements and the non-etched surface contains a bonding surface. The non-etched surface is located at a predetermined height f...	02/03/2004
6680520	Method and structure for forming precision MIM fusible circuit elements using fuses and antifuses The present invention describes an apparatus and method for fabrication of a precision circuit elements. In particular, the circuit elements are fabricated as part of an integrated circuit assembly. The processing of the circuit elements is such to provid...	01/20/2004
6639280	Semiconductor device and semiconductor chip using SOI substrate A laminated substrate is formed by laminating a device formation layer made of single crystalline semiconductor on a supporting substrate made of single crystalline semiconductor via an insulating layer with making one direction of a crystallographic axis...	10/28/2003
6614073	SEMICONDUCTOR CHIP WITH A BASE ELECTRODE AND AN EMITTER ELECTRODE EXPOSED ON ONE OF A PAIR OF OPPOSITE LATERAL FACES AND A COLLECTOR ELECTRODE EXPOSED ON A REMAINING ONE OF THE PAIR OF THE OPPOSITE LATERAL FACES A semiconductor chip provided, at a lateral face thereof, with an electrode for external electric connection. Where a semiconductor chip has a plurality of electrodes, all the electrodes are preferably formed at one or more lateral faces of the semiconduc...	09/02/2003
6537895	Method of forming shallow trench isolation in a silicon wafer A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches are formed in a silicon ...	03/25/2003
6528858	MOSFETs with differing gate dielectrics and method of formation A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is als...	03/04/2003
6525403	Semiconductor device having MIS field effect transistors or three-dimensional structure A semiconductor projection is formed on a semiconductor substrate of the first conductivity type and has a semiconductor layer of the first conductivity type. The semiconductor projection has a top surface and side surfaces. A gate electrode is formed abo...	02/25/2003
6433402	Selective copper alloy deposition Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited ...	08/13/2002
6424048	Semiconductor chip, semiconductor device, circuit board and electronic equipment and production methods for them A semiconductor chip having a vertical current conduction structure of a high aspect ratio and high reliability: a semiconductor device, a circuit substrate, and an electronic apparatus each containing such semiconductor chips; and a method for producing ...	07/23/2002
6417571	Single grain copper interconnect with bamboo structure in a trench A system and method for providing copper interconnect in a trench formed in a dielectric is disclosed. In one aspect, the method and system include providing a copper layer; removing a portion of the copper layer outside of the trench; annealing the coppe...	07/09/2002
6285073	Contact structure and method of formation The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isola...	09/04/2001
6242788	Semiconductor device and a method of manufacturing the same In a semiconductor device, a first trench having a uniformly inclined surface at a predetermined angle is formed downward from the surface of a semiconductor substrate. A second trench is formed vertically downward from the first trench. These trenches ar...	06/05/2001
6214698	Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and ...	04/10/2001
6040597	Isolation boundaries in flash memory cores A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of ...	03/21/2000
5854509	Method of fabricating semiconductor device and semiconductor device Ordinary anisotropic etching is performed up to a depth (d1) while anisotropic etching is performed to form an inward taper from the depth (d1) by changing etching conditions such as components in a vapor phase and the temperature of a silicon substrate (...	12/29/1998

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Class 257/521 - Sides of grooves along major crystal planes (e.g., (111), (100) planes, etc.)