Bizarre Patents
Decorative Jeweled Wheel Cover
An improved wheel is provided wherein decorative items such as gem stones are embedded in either the wheel surface, a special mounting section attached to the wheel surface, or to a spoke strap that wraps around each spoke and positions embedded gem stones on the outside surface of the spoke.
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| Number | Title | Issue Date |
| 7728404 | Punchthrough diode and method of manufacturing thereof A semiconductor device includes a substrate of a first conductivity type, and a first semiconductor region that includes a plurality of sub-regions of the first conductivity type that have a first doping concentration and a further semiconductor region of a second c... | 06/01/2010 |
| 7482669 | Semiconductor device and method of manufacturing such a device The invention relates to a so-termed punchthrough diode (10) with a stack of, for example, n++, n−, p+, n++ regions (1,2,3,4). In the known diode, these semiconductor regions (1,2,3,4) are positioned in said order on a substrate (11). T... | 01/27/2009 |
| 7321138 | Planar diac The invention concerns an asymmetric diac comprising a highly-doped substrate (21) of a first type of conductivity, a lightly-doped epitaxial layer (22) of the second type of conductivity on the upper surface of the substrate (21), a highly-dope... | 01/22/2008 |
| 7262110 | Trench isolation structure and method of formation In general, the present invention discloses at least one trench isolation region formed in a semiconductor substrate to electrically and/or optically isolate at least one active region from another active region. The at least one trench isolation region comprises a ... | 08/28/2007 |
| 7245027 | Apparatus and method for signal bus line layout in semiconductor device A device and method for layout and fabrication of power supply bus lines in an integrated circuit such as a memory circuit are described. In accordance with the present invention, power bus lines and bonding pads of the circuit are not necessarily formed in both edg... | 07/17/2007 |
| 7244970 | Low capacitance two-terminal barrier controlled TVS diodes A two-terminal barrier controlled TVS diode has a depletion region barrier blocking majority carrier flow through the channel region at the vicinity of the cathode region at bias levels below the predetermined clamping voltage applied between the anode electrode and... | 07/17/2007 |
| 7190049 | Nanocylinder arrays Pathways to rapid and reliable fabrication of nanocylinder arrays are provided. Simple methods are described for the production of well-ordered arrays of nanopores, nanowires, and other materials. This is accomplished by orienting copolymer films and removing a comp... | 03/13/2007 |
| 7164183 | Semiconductor substrate, semiconductor device, and method of manufacturing the same A semiconductor device includes a porous layer, a structure which is formed on the porous layer and has a semiconductor region whose height of the sectional shape is larger than the width, and a strain inducing region which strains the structure by applying stress t... | 01/16/2007 |
| 7138699 | Semiconductor integrated circuit and noncontact information medium A semiconductor integrated circuit includes a supply voltage generator for rectifying a signal received by an antenna coil and generating a supply voltage set at a predetermined voltage by a regulator, and a demodulator. The demodulator includes a demodulation circu... | 11/21/2006 |
| 7126191 | Double-diffused semiconductor device A DMOSFET and a method of fabricating the same, capable of keeping a desirable level of drain voltage resistance and, at the same time, of reducing the drain resistance. In a DMOSFET configured as having a drain region composed of an epitaxial layer formed on a P-ty... | 10/24/2006 |
| 7009255 | Semiconductor device having punch-through structure off-setting the edge of the gate electrodes A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 03/07/2006 |
| 6963094 | Metal oxide semiconductor transistors having a drain punch through blocking region and methods for fabricating metal oxide semiconductor transistors having a drain punch through blocking region Metal oxide semiconductor transistors and devices with such transistors and methods of fabricating such transistors and devices are provided. Such transistors may have a silicon well region having a first surface and having spaced apart source and drain regions ther... | 11/08/2005 |
| 6949439 | Semiconductor power component and a method of producing same A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate... | 09/27/2005 |
| 6949423 | MOSFET-fused nonvolatile read-only memory cell (MOFROM) With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard C... | 09/27/2005 |
| 6936892 | Semiconductor device with alternating conductivity type layer and method of manufacturing the same A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. T... | 08/30/2005 |
| 6933215 | Process for doping a semiconductor body In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relat... | 08/23/2005 |
| 6919625 | Surface mount multichip devices A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame... | 07/19/2005 |
| 6897095 | Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first ... | 05/24/2005 |
| 6833594 | Semiconductor integrated circuit device and manufacture method therefore A submicron CMOS transistor is mounted on the same substrate together with an analog CMOS transistor, a high voltage-resistance MOS transistor, a bipolar transistor, a diode, or a diffusion resistor, without degrading the characteristics of these components. When a ... | 12/21/2004 |
| RE38608 | Low-voltage punch-through transient suppressor employing a dual-base structure A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p− region ab... | 10/05/2004 |
| 6791411 | Power amplifier and a method for operating a power amplifier According to the invention, the high-frequency power amplifier is characterised in that the power transistor is switched in such a way that said transistor is operated in the breakdown region and that a control loop is provided. Charge carriers that are produced is ... | 09/14/2004 |
| 6602769 | Low-voltage punch-through bi-directional transient-voltage suppression devices and methods of making the same A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adja... | 08/05/2003 |
| 6600204 | Low-voltage punch-through bi-directional transient-voltage suppression devices having surface breakdown protection and methods of making the same A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivi... | 07/29/2003 |
| 6597052 | Punch-through diode having an inverted structure The invention relates to a so-called punch-through diode comprising a stack of, for example, an n++, p-, p+, n++ region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (1... | 07/22/2003 |
| 6534834 | Polysilicon bounded snapback device A snapback device functions as a semiconductor protection circuit to prevent damage to integrated circuits due to events such as electrostatic discharge and the like. The snapback device is capable of carrying considerable current at a reduced voltage onc... | 03/18/2003 |
| 6528858 | MOSFETs with differing gate dielectrics and method of formation A semiconductor wafer including an NMOS device and a PMOS device. The NMOS device is formed to have a high-K gate dielectric and the PMOS device is formed to have a standard-K gate dielectric. A method of forming the NMOS device and the PMOS device is als... | 03/04/2003 |
| 6489660 | Low-voltage punch-through bi-directional transient-voltage suppression devices A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adja... | 12/03/2002 |
| 6459133 | Enhanced flux semiconductor device with mesa and method of manufacturing same The invention relates to a so-called punch-through diode with a mesa (12) comprising, in succession, a first (1), a second (2) and a third (3) semiconductor region (1) of, respectively, a first, a second and the first conductivity type, which punch-throug... | 10/01/2002 |
| 6388302 | Ground compatible inhibit circuit The invention relates to a ground-compatible inhibit circuit structure and method, for circuits integrated in a semiconductor substrate which is unrelated to ground potential. The circuit structure is integrated in the same substrate as an associated circ... | 05/14/2002 |
| 6388319 | Three commonly housed diverse semiconductor dice A semiconductor device includes: at least first, second, and third semiconductor dice, each having opposing surfaces which contain respective electrodes; a conductive lead frame including first and second separate die pad areas, the first and second semic... | 05/14/2002 |
| 6369440 | Semiconductor substrate and manufacturing method thereof A semiconductor apparatus substrate according to the present invention has a substrate, a piece-substrate that has been punched out of the substrate and pushed back to the original position, an opening unit formed in a region of the substrate that substan... | 04/09/2002 |
| 6344658 | Gunn diode, NRD guide gunn oscillator, fabricating method of gunn diode and structure for assembly of the same A Gunn diode which is formed by sequentially laminating a first semiconductor layer, an active layer and a second semiconductor layer onto a semiconductor substrate. The Gunn diode comprises first and second electrodes arranged on the second semiconductor... | 02/05/2002 |
| 6300656 | Nonvolatile semiconductor memory device having a drain region of different impurity density and conductivity types A nonvolatile semiconductor memory device includes an n-type region which is in contact with n+ drain diffusion region at a surface of p-type silicon substrate and covers the periphery thereof. The device also includes a p-type impurity region ... | 10/09/2001 |
| 6297552 | Commonly housed diverse semiconductor die A MOSFET die and a Schottky diode die are mounted on a common lead frame pad and their drain and cathode, respectively, are connected together at the pad. The pad has a plurality of pins extending from one side thereof. The lead frame has insulated pins o... | 10/02/2001 |
| 6262466 | Lateral semiconductor structure for forming a temperature-compensated voltage limitation A lateral semiconductor structure having a punch-through diode for forming a temperature-compensated voltage limitation in which the space charge resistance is reduced through a lateral arrangement of preferably annular regions around a base trough. This ... | 07/17/2001 |
| 6200841 | MOS transistor that inhibits punchthrough and method for fabricating the same A MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled wit... | 03/13/2001 |
| 6188110 | Integration of isolation with epitaxial growth regions for enhanced device formation A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to f... | 02/13/2001 |
| 6172402 | Integrated circuit having transistors that include insulative punchthrough regions and method of formation An integrated circuit includes a plurality of transistors formed to include insulative punchthrough regions. Each of the plurality of transistors includes a channel formed upon a substrate, an insulative punchthrough region formed below the channel, a sou... | 01/09/2001 |
| 6015999 | Low-voltage punch-through transient suppressor employing a dual-base structure A punch-through diode transient suppression device has a base region of varying doping concentration to improve leakage and clamping characteristics. The punch-through diode includes a first region comprising an n+ region, a second region comprising a p- ... | 01/18/2000 |
| 5994760 | Device having a low threshold voltage for protection against electrostatic discharges The present invention relates to an assembly of two pairs of diodes in a single semiconductor substrate of a first type of conductivity, the first pair including a first diode in series with a second diode, the second pair including a third diode in serie... | 11/30/1999 |
