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A self defense weapon formed as a memo pad and which is easily held by a person's fingers, therefore making it possible to provide protection from a mugger and also to quickly and easily write a record or a message without failure of missing or forgetting significant information under a stressful situation.
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| Number | Title | Issue Date |
| 8188469 | Test device and a semiconductor integrated circuit device A test device includes a semiconductor substrate having a first test region and a second test region defined thereon, wherein a layout of the first test region includes first active regions separated from each other by isolation regions in the semiconductor substrat... | 05/29/2012 |
| 8183565 | Programmable resistance memory array with dedicated test cell A rewritable nonvolatile memory includes a test cell that is dedicated to testing the storage characteristics of other, similar, storage cells formed within the same integrated circuit memory. The test cell may be share the same structure and composition as storage ... | 05/22/2012 |
| 8178876 | Method and configuration for connecting test structures or line arrays for monitoring integrated circuit manufacturing A test chip comprises at least one level having an array of regions. Each region is capable of including at least one test structure. At least some of the regions include respective test structures. The level has a plurality of driver lines that provide input signal... | 05/15/2012 |
| 8174010 | Unified test structure for stress migration tests A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an i... | 05/08/2012 |
| 8174282 | Leak current detection circuit, body bias control circuit, semiconductor device, and semiconductor device testing method A leak current detection circuit that improves the accuracy for detecting a leak current in a MOS transistor without enlarging the circuit scale. The leak current detection circuit includes at least one P-channel MOS transistor which is coupled to a high potential p... | 05/08/2012 |
| 8174011 | Positional offset measurement pattern unit featuring via-plug and interconnections, and method using such positional offset measurement pattern unit In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconn... | 05/08/2012 |
| 8169230 | Semiconductor device and method of testing the same A semiconductor device is formed on a semiconductor wafer. The semiconductor device has: an output buffer configured to externally output an output signal received from an internal circuit; an input buffer configured to output an input signal externally received to ... | 05/01/2012 |
| 8168970 | Die having embedded circuitry with test and test enable circuitry Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits w... | 05/01/2012 |
| 8164091 | Multi-purpose poly edge test structure Multi-purpose poly edge test structure. According to an embodiment, the present invention provides a test structure. The test structure includes a doped silicon substrate, the doped silicon substrate being grounded, the doped silicon substrate including a first gate... | 04/24/2012 |
| 8159252 | Test handler and method for operating the same for testing semiconductor devices A test handler and method for operating a test handler for testing semiconductor devices are provided. The test handler includes a test tray located on one side of an opening apparatus in which a plurality of inserts are arrayed, wherein each insert comprises at lea... | 04/17/2012 |
| 8159254 | Crack sensors for semiconductor devices Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimet... | 04/17/2012 |
| 8154019 | Semiconductor apparatus and calibration method thereof A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison ... | 04/10/2012 |
| 8143619 | Methods of combinatorial processing for screening multiple samples on a semiconductor substrate In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for s... | 03/27/2012 |
| 8138497 | Test structure for detecting via contact shorting in shallow trench isolation regions A test structure for detecting void formation in semiconductor device layers includes a plurality of active device areas formed in a substrate, a plurality of shallow trench isolation (STI) regions separating the active device areas, a plurality of gate electrode st... | 03/20/2012 |
| 8138498 | Apparatus and methods for determining overlay of structures having rotational or mirror symmetry Disclosed are overlay targets having flexible symmetry characteristics and metrology techniques for measuring the overlay error between two or more successive layers of such targets. Techniques for imaging targets with flexible symmetry characteristics and analyzing... | 03/20/2012 |
| 8120026 | Testing wiring structure and method for forming the same The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate la... | 02/21/2012 |
| 8120024 | Semiconductor package having test pads on top and bottom substrate surfaces and method of testing same A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on ... | 02/21/2012 |
| 8115202 | Thin film transistor array substrate and electronic ink display device A thin film transistor array substrate suitable for being applied in an electronic ink display device is provided. The thin film transistor array substrate includes a substrate, scan lines, data lines, thin film transistors, pixel electrodes and testing signal lines... | 02/14/2012 |
| 8106396 | Thin film transistor array substrate A thin film transistor array substrate includes a substrate having a display area and a peripheral area, a plurality of pixel units, a plurality of signal lines, and a testing circuit. The signal lines are electrically connected with the pixel units disposed in the ... | 01/31/2012 |
| 8106395 | Semiconductor device and method of manufacturing the same A technique of manufacturing a semiconductor device capable of performing a probe test by a common test apparatus as normal LSI chips even for large-area chips is provided. A chip comprising a device formed on a device area by a semiconductor process and including a... | 01/31/2012 |
| 8084769 | Testkey design pattern for gate oxide A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of... | 12/27/2011 |
| 8084770 | Test structures for development of metal-insulator-metal (MIM) devices In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer betwe... | 12/27/2011 |
| 8080823 | IC chip package and image display device incorporating same A liquid crystal driver mounting package in accordance with an embodiment of the present invention contains a film base material and a liquid crystal driver connected to each other via an interposer. The liquid crystal driver includes first alignment marks on its fa... | 12/20/2011 |
| 8076951 | Spray cooling thermal management system and method for semiconductor probing, diagnostics, and failure analysis A micro-spray cooling system beneficial for use in testers of electrically stimulated integrated circuit chips is disclosed. The system includes micro-spray heads disposed about a probe head. The spray heads and probe head are disposed in a sealed manner inside a sp... | 12/13/2011 |
| 8067769 | Wafer level package structure, and sensor device obtained from the same package structure A wafer level package structure with a plurality of compact sensors such as acceleration sensors and gyro sensors is provided. This package structure is composed of a semiconductor wafer with plural sensor units, and a pair of package wafers bonded to both surfaces ... | 11/29/2011 |
| 8063401 | Testing for correct undercutting of an electrode during an etching step A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bo... | 11/22/2011 |
| 8063402 | Integrated circuit having a filler standard cell An integrated circuit includes a functional block having a plurality of standard cells. The plurality of standard cells includes a plurality of functional standard cells and a filler standard cell. Each functional standard cell of the plurality of functional standar... | 11/22/2011 |
| 8058648 | Switching device and testing apparatus There is provided a switching device that electrically connects or disconnects a first terminal and a second terminal to/from each other. The switching device includes a semiconductor layer, a drain electrode that is formed in the semiconductor layer, where the drai... | 11/15/2011 |
| 8053774 | Method and apparatus to fabricate polymer arrays on patterned wafers using electrochemical synthesis A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to co... | 11/08/2011 |
| 8049213 | Feature dimension measurement A method of measuring dimensional characteristics includes providing a substrate and forming a reflective layer over the substrate. A dielectric layer is then formed over the reflective layer. The dielectric layer includes a grating pattern and a resistivity test li... | 11/01/2011 |
| 8049214 | Degradation correction for finFET circuits A pair of split-gate fin field effect transistors (finFETs) in an IC, each containing a signal gate and a control gate, in which an adjustable voltage source, preferably in the form of a digital-to-analog-converter (DAC), is connected to the control gate of one of t... | 11/01/2011 |
| 8044394 | Semiconductor wafer with electrically connected contact and test areas The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, w... | 10/25/2011 |
| 8044395 | Semiconductor memory apparatus for controlling pads and multi-chip package having the same A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide fir... | 10/25/2011 |
| 8044396 | Semiconductor device and method of designing the same A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed ... | 10/25/2011 |
| 8039837 | In-line voltage contrast detection of PFET silicide encroachment A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the b... | 10/18/2011 |
| 8030650 | Pixel structure and methods for fabricating, detecting, and repairing the pixel structure A pixel structure comprises at least two scan and data lines. The scan and data lines substantially intersects one another to form at least one region therein. The pixel structure further comprises at least one thin film transistor, at least one passivation layer, a... | 10/04/2011 |
| 8030649 | Scan testing in single-chip multicore systems Various techniques for testing multicore processors in an integrated circuit. Each core includes a plurality of registers configured to form at least two scan chains. In one embodiment, a verification unit located in the integrated circuit is electrically coupled to... | 10/04/2011 |
| 8026515 | Platform-independent system and method for controlling a temperature of an integrated circuit A platform-independent temperature controller system and method are provided. Included is a sensor is in communication with an integrated circuit. Further, a platform-independent temperature controller is in communication, with the sensor for controlling a temperatu... | 09/27/2011 |
| 8026516 | Carrier module for use in a handler and handler for handling packaged chips for a test using the carrier modules Provided is a carrier module for use in a handler for handling a packaged chip for a test, the carrier module including a body provided, a base plate where the packaged chips are placed, provided to the body, and at least one latch which holds the packaged chips in ... | 09/27/2011 |
| 8022403 | Semiconductor apparatus including photodiode unit and method of inspection of the same A semiconductor apparatus has a light-receiving element. The light-receiving element has a photodiode unit having a shield film for removing noise, at least two test pads, and a shield film pseudo pattern which is formed by the same membranous type as the shield fil... | 09/20/2011 |
