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| Number | Title | Issue Date |
| 8188550 | Integrated circuit structure with electrical strap and its method of forming A method of forming an IC is presented. The method includes providing a substrate having a plurality of transistors formed thereon. The transistors have gate stack, source and drain regions. An electrical strap is formed and in contact with at least a portion of at ... | 05/29/2012 |
| 8102011 | Semiconductor device including a field effect transistor and method for manufacturing the same There is provided a semiconductor device including a field effect transistor. The field effect transistor includes a p-type low concentration region formed over a surface of a substrate, an n-type drain-side diffusion region and an n-type source-side diffusion regio... | 01/24/2012 |
| 7400018 | End of range (EOR) secondary defect engineering using chemical vapor deposition (CVD) substitutional carbon doping A method for incorporating carbon into a wafer at the interstitial a-c silicon interface of the halo doping profile is achieved. A bulk silicon substrate is provided. A carbon-doped silicon layer is deposited on the bulk silicon substrate. An epitaxial silicon layer... | 07/15/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7289375 | Data holding circuit A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a tim... | 10/30/2007 |
| 7276750 | Semiconductor device having trench capacitor and fabrication method for the same A semiconductor device includes a semiconductor substrate with a trench; a capacitor; a collar oxide film arranged on a portion of a side of the trench above the capacitor; a storage node arranged on a side of the collar oxide film in an upper portion of the trench ... | 10/02/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7205593 | MOS image pick-up device and camera incorporating the same A MOS image pick-up device including a semiconductor substrate, an imaging region formed on the semiconductor substrate by arraying plural unit pixels, and a peripheral circuit region including a driving circuit for operating the imaging region formed on the semicon... | 04/17/2007 |
| 7199410 | Pixel structure with improved charge transfer An active pixel is described comprising a semiconductor substrate and a radiation sensitive source of carriers in the substrate, such as for instance, a photodiode. A non-carrier storing, carrier collecting region in the substrate is provided for attracting carriers... | 04/03/2007 |
| 7198968 | Method of fabricating thin film transistor array substrate A method of fabricating a thin film transistor array substrate is provided. The method includes forming a first conductive pattern group on a substrate using a first etch resist and a first soft mold, the first conductive pattern group including a gate electrode and... | 04/03/2007 |
| 7193275 | Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonunif... | 03/20/2007 |
| 7193276 | Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion ... | 03/20/2007 |
| 7166515 | Implanted hidden interconnections in a semiconductor device for preventing reverse engineering A camouflaged interconnection for interconnecting two spaced-apart regions of a common conductivity type in an integrated circuit or device and a method of forming same. The camouflaged interconnection comprises a first region forming a conducting channel between th... | 01/23/2007 |
| 7151301 | Sensitivity enhanced biomolecule field effect transistor There is provided a biomolecule FET enhancing a sensitivity. The biomolecule FET includes a substrate, first and second impurity regions formed on both sides of the substrate, and doped with impurities of a polarity opposite to that of the substrate, a gate formed o... | 12/19/2006 |
| 7049667 | Conductive channel pseudo block process and circuit to inhibit reverse engineering A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having a controlled outline. A layer of conductive material having a controlled outline is disposed among... | 05/23/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7008873 | Integrated circuit with reverse engineering protection Technique and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of layers of material having controlled outlines and controlled thicknesses. A layer of dielectric material of a controlled thickness... | 03/07/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6979606 | Use of silicon block process step to camouflage a false transistor A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is n... | 12/27/2005 |
| 6972460 | Semiconductor device and manufacturing method thereof A semiconductor device including a drift layer of a first conductivity type formed on a surface of a semiconductor substrate. A surface of the drift layer has a second area positioned on an outer periphery of a first area. A cell portion formed in the first area inc... | 12/06/2005 |
| 6953961 | DRAM structure and fabricating method thereof A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure.... | 10/11/2005 |
| 6924552 | Multilayered integrated circuit with extraneous conductive traces A multilayered integrated circuit and a method of designing a multilayered integrated circuit are provided. The circuit comprises at least two conductive layers and extraneous conductive lines placed in the conductive layers. The extraneous conductive lines are made... | 08/02/2005 |
| 6921687 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer,... | 07/26/2005 |
| 6914299 | Horizontal surrounding gate MOSFETs A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely dis... | 07/05/2005 |
| 6894354 | Trench isolated transistors, trench isolation structures, memory cells, and DRAMs An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 05/17/2005 |
| 6841837 | Semiconductor device A semiconductor device has: a gate insulator film of a transistor formed in a predetermined region on a region of a first conductivity type; a gate electrode of the transistor formed on the gate insulator film; a diffusion layer of a second conductivity type formed ... | 01/11/2005 |
| 6806541 | Field effect transistor with improved isolation structures An electronic device architecture is described comprising a field effect device in an active region 22 of a substrate 10. Channel stop implant regions 28a and 28b are used as isolation structures and are spaced apart from th... | 10/19/2004 |
| 6800909 | Semiconductor device and method of manufacturing the same There are provided a gate electrode formed on a semiconductor substrate of one conductivity type via a gate insulating film, ion-implantation controlling films formed on both side surfaces of the gate electrode and having a space between the gate electrode and an up... | 10/05/2004 |
| 6737724 | Semiconductor device and method of manufacturing the same Disclosed is a semiconductor device including a transistor structure including an epitaxial silicon layer formed on a main surface of an n-type semiconductor substrate, source-drain diffusion layers formed on at least the epitaxial silicon layer, a channel region fo... | 05/18/2004 |
| 6690074 | Radiation resistant semiconductor device structure A semiconductor device structure is described for reducing radiation induced current flow caused by incident ionizing radiation. The structure comprises a semiconductor substrate; two or more regions of a first conductivity type in the substrate; and a gu... | 02/10/2004 |
| 6545318 | Semiconductor device and manufacturing method thereof An impurity layer is formed between a semiconductor substrate and a buried oxide film in an SOI substrate composed of the semiconductor substrate, the buried oxide film and a semiconductor layer.... | 04/08/2003 |
| 6501155 | Semiconductor apparatus and process for manufacturing the same To provide a semiconductor apparatus that secures high ESD protection capability and yet reduces leak current. Cut sections 64-1 and 64-2 are provided in end sections of a second edge 62 of a drain region 22. When a distance between a first edge 60 of a source... | 12/31/2002 |
| 6489657 | Semiconductor device with improved channel stopper A semiconductor device comprising a high withstand voltage MOS transistor of an offset drain/offset source structure easing a high electric field generated between a channel and a parasitic channel stopper in an operating state and preventing changes of a... | 12/03/2002 |
| 6452219 | Insulated gate bipolar transistor and method of fabricating the same An IGBT having a buffer layer for shortening the turn-off time and for preventing the latching up is improved. The buffer layer of the present invention is not bare at the edge of a diced cross-section of the IGBT chip. According to this construction, a w... | 09/17/2002 |
| 6417538 | Nonvolative semiconductor memory device with high impurity concentration under field oxide layer Flash type programmable nonvolatile memory unit cells are provided, along with a manufacturing method. Each unit cell is formed such that the interpoly dielectric layer and the control gate surround the top surface and also the four lateral surfaces of th... | 07/09/2002 |
| 6376296 | High-voltage device and method for manufacturing high-voltage device A high-voltage device. A substrate has a first conductive type. A first well region with the first conductive type is located in the substrate. A second well region with the second conductive type is located in the substrate but is isolated from the first... | 04/23/2002 |
| 6369433 | High voltage transistor with low body effect and low leakage A high voltage transistor exhibiting low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a field implant blocking mask over the channel area, thereby producing a transistor wi... | 04/09/2002 |
| 6365945 | Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insu... | 04/02/2002 |
