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| Number | Title | Issue Date |
| 8039904 | Apparatus of memory array using finfets A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. ... | 10/18/2011 |
| 7960799 | Semiconductor device and method for manufacturing the same A charge trap type non-volatile memory device has memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend. Each of the memory cells has a tunnel insulating film formed ... | 06/14/2011 |
| 7888749 | Semiconductor devices having selectively tensile stressed gate electrodes and methods of fabricating the same A semiconductor device includes an active region. A gate electrode is disposed on the active region. An isolation region adjoins the active region, and is recessed with respect to a top surface of the active region underlying the gate electrode. The isolation region... | 02/15/2011 |
| 7808055 | Methods and apparatus for semiconductor memory devices manufacturable using bulk CMOS process manufacturing The present invention discloses semiconductor devices that can be manufactured utilizing standard process of manufacturing and that can hold information. In accordance with a presently preferred embodiment of the present invention, one or more semiconductor devices ... | 10/05/2010 |
| 7709906 | Semiconductor device and method of fabricating the same A semiconductor device includes a gate insulation film provided on a semiconductor substrate, a gate electrode provided on the gate insulation film, a pair of first diffusion layers, a pair of second diffusion layers which are provided in the semiconductor substrate... | 05/04/2010 |
| 7528454 | Semiconductor memory with sense amplifier The present invention provides a semiconductor memory which has sense amplifiers, each including a pair of MOSFETs having complete symmetry in regard to not only the shape but also to the impurity profile in a diffusion layer, and the present invention is also capab... | 05/05/2009 |
| 7442985 | Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same An element isolating region for separating an element region of a semiconductor layer is formed in a peripheral circuit section of a semiconductor memory device, and a first conductive layer is formed with the element region with a first insulating film interposed t... | 10/28/2008 |
| 7391087 | MOS transistor structure and method of fabrication An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or sili... | 06/24/2008 |
| 7372734 | Methods of operating electrically alterable non-volatile memory cell A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a ... | 05/13/2008 |
| 7351661 | Semiconductor device having trench isolation layer and a method of forming the same A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer fo... | 04/01/2008 |
| 7348628 | Vertical channel semiconductor devices and methods of manufacturing the same Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the uppe... | 03/25/2008 |
| 7342272 | Flash memory with recessed floating gate A flash memory device where the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substr... | 03/11/2008 |
| 7341904 | Capacitorless 1-transistor DRAM cell and fabrication method A semiconductor device is fabricated by forming a trench in a semiconductor body. A region of dielectric material is formed within at least a lower portion of the trench. An upper portion of the semiconductor body is doped. A cutout is formed in the semiconductor ma... | 03/11/2008 |
| 7335565 | Metal-oxide-semiconductor device having improved performance and reliability A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and... | 02/26/2008 |
| 7332398 | Manufacture of trench-gate semiconductor devices A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and t... | 02/19/2008 |
| 7332409 | Methods of forming trench isolation layers using high density plasma chemical vapor deposition A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed. ... | 02/19/2008 |
| 7329921 | Lateral semiconductor transistor A lateral semiconductor transistor is disclosed. In one embodiment, the transistor includes a semiconductor body, in which a source region, a body region and a drain region, a drift region extending in the lateral direction between body region and drain region, and ... | 02/12/2008 |
| 7323386 | Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region m... | 01/29/2008 |
| 7323394 | Method of producing element separation structure A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an... | 01/29/2008 |
| 7320926 | Shallow trench filled with two or more dielectrics for isolation and coupling for stress control A method for forming shallow trenches having different trench fill materials is described. A stop layer is provided on a substrate. A plurality of trenches is etched through the stop layer and into the substrate. A first layer is deposited over the stop layer and fi... | 01/22/2008 |
| 7319062 | Trench isolation method with an epitaxially grown capping layer A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating materi... | 01/15/2008 |
| 7307324 | MOS transistor in an active region After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon ... | 12/11/2007 |
| 7294903 | Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ... | 11/13/2007 |
| 7285495 | Methods for thermally treating a semiconductor layer A method for thermally treating a semiconductor layer is described. An embodiment of the technique includes implanting atomic species into a first surface of a donor wafer to form a zone of weakness at a predetermined depth that defines the thickness of a transfer l... | 10/23/2007 |
| 7282412 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/16/2007 |
| 7282449 | Thermal treatment of a semiconductor layer A method for thermally treating a silicon germanium semiconductor layer from a donor wafer is described. An embodiment of the technique includes co-implanting atomic species into a first surface of the donor wafer to form a zone of weakness at a predetermined depth ... | 10/16/2007 |
| 7279393 | Trench isolation structure and method of manufacture therefor The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask... | 10/09/2007 |
| 7276411 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 10/02/2007 |
| 7276428 | Methods for forming a semiconductor structure Methods for forming a semiconductor structure are described. In an embodiment, the technique includes providing a donor wafer having a first semiconductor layer and a second semiconductor layer on the first layer and having a free surface, implanting atomic species ... | 10/02/2007 |
| 7268402 | Memory cell with trench-isolated transistor including first and second isolation trenches An isolation trench in a semiconductor includes a first isolation trench portion having a first depth and having a first sidewall intersecting a surface of the semiconductor at a first angle. A second isolation trench portion extends within and below the first isola... | 09/11/2007 |
| 7267037 | Bidirectional singulation saw and method A singulation saw for sawing either substrate or wafers includes a pair of counter-rotating saw blades mounted for independent movement in a vertical direction for alternatively engaging with a substrate to be singulated. The singulation saw further includes a trans... | 09/11/2007 |
| 7268395 | Deep trench super switch device A deep trench super switch device has a plurality of trenches, each of the trenches containing a gate electrode polysilicon layer on top of a plurality of stacked conductive floating polysilicon layers, the remainder of each of the trenches being filled with a nonco... | 09/11/2007 |
| 7238568 | Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described... | 07/03/2007 |
| 7221030 | Semiconductor device A pad oxide film and a silicon nitride film are formed on a semiconductor substrate. Next, after the patterning of the silicon nitride film, by etching the pad oxide film and the substrate, a first trench is formed in a first region and a second trench is formed in ... | 05/22/2007 |
| 7208812 | Semiconductor device having STI without divot and its manufacture The method of manufacturing a semiconductor device has the steps of: etching a semiconductor substrate to form an isolation trench by using as a mask a pattern including a first silicon nitride film and having a window; depositing a second silicon nitride film cover... | 04/24/2007 |
| 7202102 | Doped absorption for enhanced responsivity for high speed photodiodes A photodiode with a semiconductor intrinsic light absorption layer has at least one p-doped light absorption layer or an n-doped light absorption layer, and preferably both. The diode also has a cathode electrode and an anode electrode electrically coupled with the ... | 04/10/2007 |
| 7196381 | Corner protection to reduce wrap around A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequ... | 03/27/2007 |
| 7189606 | Method of forming fully-depleted (FD) SOI MOSFET access transistor A fully-depleted (FD) Silicon-on-Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions and a method of fabrication are disclosed. ... | 03/13/2007 |
| 7183610 | Super trench MOSFET including buried source electrode and method of fabricating the same In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias o... | 02/27/2007 |
| 7160780 | Method of manufacturing a fin field effect transistor In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose ... | 01/09/2007 |
