Bizarre Patents
Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| 8129799 | Semiconductor device A field-effect transistor (142) includes a lowly p-doped region 110 formed on a surface of a substrate (102), an n-doped drain region 112 and n-doped source region 114 arranged on a surface of the lowly p-doped region 110, a... | 03/06/2012 |
| 8093663 | Semiconductor device, method of fabricating the same, and patterning mask utilized by the method A semiconductor device. The device comprises an active region isolated by an isolation structure on a substrate. The device further comprises a gate electrode extending across the active area and overlying the substrate, a pair of source region and drain region, dis... | 01/10/2012 |
| 7825479 | Electrical antifuse having a multi-thickness dielectric layer An electrical antifuse comprising a field effect transistor includes a gate dielectric having two gate dielectric portions. Upon application of electric field across the gate dielectric, the magnitude of the electrical field is locally enhanced at the boundary betwe... | 11/02/2010 |
| 7791147 | MOS device resistant to ionizing radiation An embodiment of a MOS device resistant to ionizing-radiation, has: a surface semiconductor layer with a first type of conductivity; a gate structure formed above the surface semiconductor layer, and constituted by a dielectric gate region and a gate-electrode regio... | 09/07/2010 |
| 7462916 | Semiconductor devices having torsional stresses A FET structure is provided in which at least one stressor element provided at or near one corner of an active semiconductor region applies a stress in a first direction to one side of a channel region of the FET to apply a torsional stress to the channel region of ... | 12/09/2008 |
| 7402474 | Manufacturing method of semiconductor device A method of manufacturing a semiconductor device comprises the following steps: a step of depositing a silicon oxide film on the top surface of an epitaxial layer of the region where a high withstand voltage MOS transistor is formed; a step of subsequently depositin... | 07/22/2008 |
| 7335915 | Image displaying device and method for manufacturing same A technique for improving the manufacturing yield of an image displaying device is disclosed. A fabrication method of the image displaying device includes the steps of forming on an insulative substrate a plurality of island-like semiconductor layers, forming a gate... | 02/26/2008 |
| 7329570 | Method for manufacturing a semiconductor device An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, ... | 02/12/2008 |
| 7323394 | Method of producing element separation structure A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an... | 01/29/2008 |
| 7312530 | Semiconductor device with multilayered metal pattern A semiconductor device comprises a first insulating film formed on a semiconductor substrate, a first metal pattern formed on the first insulating film, a second insulating film formed on the first metal pattern, a second metal pattern formed on the second insulatin... | 12/25/2007 |
| 7309899 | Semiconductor device including a MOSFET with nitride side wall A semiconductor device includes a semiconductor substrate, a gate insulating layer, a gate electrode structure and a side wall structure. The gate insulating layer is formed on the semiconductor substrate. The gate electrode structure is formed on the gate insulatin... | 12/18/2007 |
| 7307324 | MOS transistor in an active region After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon ... | 12/11/2007 |
| 7301209 | Semiconductor device A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film ... | 11/27/2007 |
| 7268392 | Trench gate semiconductor device with a reduction in switching loss A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insu... | 09/11/2007 |
| 7262111 | Method for providing a deep connection to a substrate or buried layer in a semiconductor device A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created ... | 08/28/2007 |
| 7253064 | Cascode I/O driver with improved ESD operation A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An sys... | 08/07/2007 |
| 7221039 | Thin film transistor (TFT) device structure employing silicon rich silicon oxide passivation layer A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of... | 05/22/2007 |
| 7217979 | Semiconductor apparatus including a radiator for diffusing the heat generated therein A semiconductor apparatus is provided that includes a radiator for efficiently radiating heat generated in a wiring layer used in a surge current path of an electrostatic discharge protection circuit, and also for protecting the wiring layer itself used as the surge... | 05/15/2007 |
| 7198968 | Method of fabricating thin film transistor array substrate A method of fabricating a thin film transistor array substrate is provided. The method includes forming a first conductive pattern group on a substrate using a first etch resist and a first soft mold, the first conductive pattern group including a gate electrode and... | 04/03/2007 |
| 7183662 | Memory devices with memory cell transistors having gate sidewell spacers with different dielectric properties A memory device, such as a DRAM, SRAM or non-volatile memory device, includes a substrate, a gate electrode disposed on the substrate, and source and drain regions in the substrate adjacent respective first and second sidewalls of the gate electrode. First and secon... | 02/27/2007 |
| 7180129 | Semiconductor device including insulating layer A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first ... | 02/20/2007 |
| 7176533 | Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug... | 02/13/2007 |
| 7164177 | Multi-level memory cell A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric la... | 01/16/2007 |
| 7164204 | Integrated circuit devices with an auxiliary pad for contact hole alignment An integrated circuit device structure which avoids misalignment when a contact hole is formed to expose a contact pad and a method of fabricating the same, are provided. The integrated circuit device includes a semiconductor substrate having a conductive region and... | 01/16/2007 |
| 7148574 | Bonding pad structure and method of forming the same A bonding pad structure and fabrication method thereof. A bonding pad is substantially surrounded and insulated by a dielectric layer, wherein the bonding pad is formed of at least one first conductive layer having a wiring layer with a stripe layout and a first edg... | 12/12/2006 |
| 7105878 | Active pixel having reduced dark current in a CMOS image sensor The active pixel includes a photodiode, a reset transistor, and a pixel output transistor. The photodiode is substantially covered with a protective structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential ... | 09/12/2006 |
| 7098102 | Shallow trench isolation structure and dynamic random access memory, and fabricating methods thereof A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching... | 08/29/2006 |
| 7049193 | Maskless middle-of-line liner deposition A process for fabricating a semiconductor structure, wherein the semiconductor structure includes a core region and a periphery region. The core region includes a plurality of transistors and the periphery region includes a plurality of transistors. The process incl... | 05/23/2006 |
| 7030498 | Semiconductor device with copper wirings having improved negative bias temperature instability (NBTI) A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer ins... | 04/18/2006 |
| 7019366 | Electrostatic discharge performance of a silicon structure and efficient use of area with electrostatic discharge protective device under the pad approach and adjustment of via configuration thereto to control drain junction resistance More efficient use of silicon area is achieved by incorporating an electrostatic discharge protective (ESDP) device beneath a pad area of a semiconductor structure. The pad area includes a substrate having a first metal layer above it. A second metal layer is above ... | 03/28/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7009262 | Semiconductor device and manufacturing method thereof A manufacturing method of a semiconductor device which can decrease the degradation of an element due to plasma in the LDD formation process is provided. The degradation of an element due to plasma is decreased by forming an element having an LDD structure according... | 03/07/2006 |
| 7002210 | Semiconductor device including a high-breakdown voltage MOS transistor On a semiconductor substrate, a well is formed. In the well, one MOS transistor including a gate electrode, a source region, a source field limiting layer and a source/drain region, and another MOS transistor including a gate electrode, a drain electrode, a drain fi... | 02/21/2006 |
| 6992325 | Active matrix organic electroluminescence display device An active matrix organic electroluminescence display device capable of maintaining the brightness of the organic light emitting diode. The active matrix organic electroluminescence display device comprises a thin film transistor and an organic light emitting diode. ... | 01/31/2006 |
| 6967344 | Multi-terminal chalcogenide switching devices Multi-terminal electronic switching devices comprising a chalcogenide material switchable between a resistive state and a conductive state. The devices include a first terminal, a second terminal and a control terminal. Application of a control signal to the control... | 11/22/2005 |
| 6958518 | Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor The present invention provides a semiconductor device and a method of manufacture therefor. The semiconductor device includes a semiconductor substrate having a gate formed there over. The semiconductor device further includes an isolation region having at least one... | 10/25/2005 |
| 6949815 | Semiconductor device with decoupling capacitors mounted on conductors A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and ... | 09/27/2005 |
| 6946712 | Magnetic memory device using SOI substrate A magnetic memory device includes an SOI substrate having a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating film, an element isolation insulating film formed ... | 09/20/2005 |
| 6927457 | Circuit structure for connecting bonding pad and ESD protection circuit A circuit structure for connecting a bonding pad with an electrostatic discharge protection circuit. The circuit structure includes a plurality of conductive layers, a first plurality of first vias, a first conductive line, a plurality of second conductive lines and... | 08/09/2005 |
| 6914295 | Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite ... | 07/05/2005 |
