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| Number | Title | Issue Date |
| 8169037 | Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error A MISFET includes a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a substrate/well of a second conductivity type. In the MISFET, first diffusion layers of the first conductivity typ... | 05/01/2012 |
| 8084831 | Semiconductor device A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gat... | 12/27/2011 |
| 8039903 | Passivated tiered gate structure transistor In various embodiments, a tiered gate structure transistor is provided including a source, a drain, and a gate between the source and the drain. The tiered gate structure transistor including a gate foot having a top portion and sidewalls. A gate head is attached to... | 10/18/2011 |
| 7420260 | Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a f... | 09/02/2008 |
| 7372438 | Electroluminescent display An electroluminescent display includes: a pixel region including devices arranged therein and adapted to emit light in response to a data signal; a scan driver adapted to supply a switching signal to a gate electrode of a first switching device; a data driver adapte... | 05/13/2008 |
| 7329926 | Semiconductor device with constricted current passage A semiconductor device including a gate located over a semiconductor substrate and a source/drain region located adjacent the gate. The source/drain region is bounded by an isolation structure that includes a constricted current passage between the gate and the sour... | 02/12/2008 |
| 7312504 | Transistor for memory device and method for manufacturing the same Disclosed is a transistor for a memory device realizing both a step-gated asymmetry transistor and a fin transistor in a cell and a method for manufacturing the same. The transistor has an active region protruding from a predetermined region of a substrate and a gro... | 12/25/2007 |
| 7312501 | Semiconductor device ON resistance and leakage current of a vertical power MOSFET are to be diminished. In a vertical high breakdown voltage MOSFET with unit MOSFETs (cells) arranged longitudinally and transversely over a main surface of a semiconductor substrate, the cells are made qua... | 12/25/2007 |
| 7301200 | Trench FET with self aligned source and contact A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with... | 11/27/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7271453 | Buried biasing wells in FETS A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in ... | 09/18/2007 |
| 7271068 | Method of manufacture of semiconductor device A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by... | 09/18/2007 |
| 7271440 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A re... | 09/18/2007 |
| 7256453 | Semiconductor device A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p+ gate and a gate electrode is formed on the bottom of the first region, the s... | 08/14/2007 |
| 7180142 | Semiconductor device The present invention provides a semiconductor device having an active region bent at right angles, wherein an interval between patterns for the active region and a gate is set larger than an arc radius of a curved portion (portion where a line is brought to arcuate... | 02/20/2007 |
| 7176527 | Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insu... | 02/13/2007 |
| 7176745 | Semiconductor device The well voltage of a CMOS circuit having low-threshold-voltage MOSFETs is controlled when the power supply is turned on, during normal operation, and when the supply voltage is cut off. The CMOS circuit can thus operate stably with lower power consumption, because ... | 02/13/2007 |
| 7176090 | Method for making a semiconductor device that includes a metal gate electrode A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider... | 02/13/2007 |
| 7157324 | Transistor structure having reduced transistor leakage attributes Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposit... | 01/02/2007 |
| 7118953 | Process of fabricating termination region for trench MIS device A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial l... | 10/10/2006 |
| 7105899 | Transistor structure having reduced transistor leakage attributes Undesirable transistor leakage in transistor structures becomes greatly reduced in substrates having a doped implant region formed via pulling back first and second layers of a process stack. A portion of the substrate, which also has first and second layers deposit... | 09/12/2006 |
| 7105901 | Semiconductor device An active area (1) is provided with a concave part in its corner portion in a shape along a plan view. An insulating film (7) encloses this active area. A gate electrode (30) is arranged on a depressed region (DR) having an edge portion which is... | 09/12/2006 |
| 7099225 | Semiconductor memory device with reduced leak current A semiconductor memory device includes a memory cell array, a decoder circuit configured to assert a decoding signal for selecting an access position in the memory cell array in response to an address signal supplied from an exterior, and a first circuit configured ... | 08/29/2006 |
| 7087958 | Termination structure of DMOS device In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon l... | 08/08/2006 |
| 7078296 | Self-aligned trench MOSFETs and methods for making the same Self-aligned trench MOSFETs and methods for manufacturing the same are disclosed. By having a self-aligned structure, the number of MOSFETS per unit area—the cell density—is increased, making the MOSFETs cheaper to produce. The self-aligned structure for the MOS... | 07/18/2006 |
| 7049668 | Gate contacting scheme of a trench MOSFET structure A trench MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structure includes crisscrossing trenches formed in a semiconductor substrate. The trenches include inner surfaces filled with conductive material which is electrically separated from the substrate ... | 05/23/2006 |
| 7049666 | Low power pre-silicide process in integrated circuit technology A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A thin in... | 05/23/2006 |
| 7045859 | Trench fet with self aligned source and contact A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with... | 05/16/2006 |
| 7042266 | Delay circuit and method A delay circuit does not lead to excessive increase in the delay time even if the source voltage drops, and enables to control the delay time from increasing. The delay circuit is designed to delay a logic signal SIN having two logic levels consisting of a low level... | 05/09/2006 |
| 7026204 | Transistor with reduced gate-to-source capacitance and method therefor A power transistor, formed from transistors connected in parallel, each transistor is formed in an active region using a relatively long gate called a gate finger that is typically formed from polysilicon that accumulates resistance over its length. To alleviate thi... | 04/11/2006 |
| 7009255 | Semiconductor device having punch-through structure off-setting the edge of the gate electrodes A semiconductor device and a method of manufacturing the same is disclosed. A trench is formed in an active region of a semiconductor substrate. A doped layer is formed on the inner walls of the trench. The trench is filled up with a first semiconductor layer. A gat... | 03/07/2006 |
| 7005347 | Structures of and methods of fabricating trench-gated MIS devices In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact bet... | 02/28/2006 |
| 6995450 | Semiconductor device with a frequency selective guard ring A ring-shaped P+ type diffusion region is formed on the top surface of a P type substrate in such a way as to surround a single internal circuit region. A shunt wiring is formed in an area including directly above the P+ type diffusion region o... | 02/07/2006 |
| 6982461 | Lateral FET structure with improved blocking voltage and on resistance performance and method In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57... | 01/03/2006 |
| 6940145 | Termination structure for a semiconductor device A semiconductor device (e.g. MOSFET or IGBT) comprises active and termination regions (1,2) formed in a semiconductor substrate (4). The substrate (4) has an upper surface and a termination including a trench (12) extending into the subst... | 09/06/2005 |
| 6927451 | Termination for trench MIS device having implanted drain-drift region A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial l... | 08/09/2005 |
| 6921687 | Power semiconductor element capable of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same In a p-type base layer of a trench IGBT comprising a p-type collector layer, an n-type base layer formed on the p-type collector layer, the p-type base layer formed on the n-type base layer, and an n-type emitter layer formed on the surface of the p-type base layer,... | 07/26/2005 |
| 6917076 | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide ... | 07/12/2005 |
| 6909142 | Semiconductor device including a channel stop structure and method of manufacturing the same It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surf... | 06/21/2005 |
| 6897526 | Semiconductor device and process for producing the same To provide a semiconductor device that can effectively suppress the short channel effect without deterioration of carrier migration, an impurity ion is added from a direction of the axis with respect to a silicon substrate on forming a punch through sto... | 05/24/2005 |
