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| Number | Title | Issue Date |
| 8188549 | Semiconductor memory device having layout area reduced A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplyin... | 05/29/2012 |
| 8169036 | Semiconductor integrated circuit device A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a... | 05/01/2012 |
| 8134213 | Static random access memory and method for manufacturing the same Disclosed is a static random access memory (SRAM), which includes first and second access transistors composed of metal oxide semiconductor (MOS) transistors, first and second drive transistors composed of MOS transistors, and first and second p-channel thin film tr... | 03/13/2012 |
| 8013399 | SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable A static random access memory cell which, on a substrate surmounted by a stack of layers, including: a first plurality of transistors situated at a given level of the stack of which at least one first access transistor and at least one second access transistor are c... | 09/06/2011 |
| 8008733 | Semiconductor device having a power cutoff transistor Disclosed herein is a semiconductor device having a power cutoff transistor including a semiconductor substrate of a first conductivity type; and first and second wells of the first conductivity type formed to be spaced from each other in the semiconductor substrate... | 08/30/2011 |
| 7973371 | Semiconductor integrated circuit device including static random access memory having diffusion layers for supplying potential to well region A static random access memory (SRAM) cell includes a first well region of a first conductivity type, a second well region of the first conductivity type, formed in a location different from a location where the first well region is formed, and a third well region of... | 07/05/2011 |
| 7964920 | Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation regi... | 06/21/2011 |
| 7936024 | Semiconductor devices having stacked structures A method of forming a semiconductor device may include forming an interlayer insulating layer on a semiconductor substrate, and the interlayer insulating layer may have a contact hole therein exposing a portion of the semiconductor substrate. A single crystal semico... | 05/03/2011 |
| 7888748 | Semiconductor memory device having layout area reduced A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplyin... | 02/15/2011 |
| 7880239 | Body controlled double channel transistor and circuits comprising the same By providing a body controlled double channel transistor, increased functionality in combination with enhanced stability may be accomplished. For instance, flip flop circuits usable for static RAM cells may be formed on the basis of the body controlled double channe... | 02/01/2011 |
| 7880238 | 2-T SRAM cell structure and method The present invention, in one embodiment, provides a memory device including a substrate including at least one device region; a first field effect transistor having a first threshold voltage and a second field effect transistor having a second threshold voltage, th... | 02/01/2011 |
| 7872315 | Electronic switching device An integrated switching device has a switching IGFET connected between a pair of main terminals, a protector IGFET connected between the drain and gate electrodes of the switching IGFET, and a gate resistor connected between a main control terminal and the gate elec... | 01/18/2011 |
| 7759743 | Semiconductor memory device having layout area reduced A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplyin... | 07/20/2010 |
| 7755148 | Semiconductor integrated circuit Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a... | 07/13/2010 |
| 7723804 | Semiconductor device, electro-optic device, and electric device A semiconductor device includes a semiconductor layer, and a first transistor and a second transistor that are formed using the semiconductor layer, wherein each conductance of the first and second transistors changes complementarily to each other according to a cur... | 05/25/2010 |
| 7679144 | Semiconductor device and method for manufacturing the same The semiconductor device includes a silicon substrate, a device isolation insulating film dividing an active region of the silicon substrate into plural pieces, a gate electrode formed on the active region, a source/drain region which is formed in the active region ... | 03/16/2010 |
| 7667276 | Semiconductor integrated circuit switch matrix There is provided a small-type semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a first semiconductor layer, a first sem... | 02/23/2010 |
| 7652337 | Nanotube-based switching element Nanotube-based switching elements and logic circuits. Under one aspect, a switching element includes an input node; an output node; a nanotube channel element comprising a ribbon of nanotube fabric; and a control electrode disposed in relation to the nanotube channe... | 01/26/2010 |
| 7595536 | Semiconductor device A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N− region formed in a surface region of a P type substrate, a P region formed... | 09/29/2009 |
| 7569899 | Semiconductor integrated circuit Logic LSI includes first power domains PD1 to PD4, thick-film power switches SW1 to SW4, and power switch controllers PSWC1 to PSWC4. The thick-film power switches are formed by thick-film power transistors manufactured in a... | 08/04/2009 |
| 7554163 | Semiconductor device A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region. ... | 06/30/2009 |
| 7541655 | Semiconductor device and wiring method for semiconductor device A semiconductor device includes: a first circuit in which a diffusion area A1, a first gate G1, a diffusion area A2, a second gate G2 and a diffusion area A3 constitute two transistors; and a second circuit in which a diffusion are... | 06/02/2009 |
| 7525163 | Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation regi... | 04/28/2009 |
| 7514757 | Memory formation with reduced metallization layers A semiconductor structure includes a static random access memory (SRAM) cell comprising a first pull-up MOS device, a first pull-down MOS device and a first pass-gate MOS device, a first metallization layer, and an inter-layer dielectric (ILD) underlying the first m... | 04/07/2009 |
| 7482660 | Nonvolatile semiconductor memory with transistor whose gate electrode has bird's beak A nonvolatile semiconductor memory according to an example of the present invention is provided with a memory cell having a floating gate electrode and a control gate electrode, and a select gate transistor having a select gate electrode and connected in series to t... | 01/27/2009 |
| 7476944 | Static random access memories including a silicon-on-insulator substrate Static random access memories (SRAMs) include a semiconductor substrate having a buried insulator in a predetermined portion of the semiconductor substrate and a silicon-on-insulator (SOI) region including a semiconductor layer on the buried insulator. A flip-flop c... | 01/13/2009 |
| 7456480 | Semiconductor device A semiconductor device includes an input terminal, a first aging device whose source is connected to the input terminal to turn on at τ1 and turn off at τ2 (>τ1), a second aging device whose source is connected to the input terminal, whose ga... | 11/25/2008 |
| 7453126 | Semiconductor memory device having layout area reduced A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplyin... | 11/18/2008 |
| 7432562 | SRAM devices, and electronic systems comprising SRAM devices The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystallin... | 10/07/2008 |
| 7411256 | Semiconductor integrated circuit device capacitive node interconnect A semiconductor integrated circuit device is provided, which involves inhibiting a pattern change in the node interconnect and an increase of number of manufacturing process, when the capacitor is additionally installed in the SRAM, while providing higher reliabilit... | 08/12/2008 |
| 7375402 | Method and apparatus for increasing stability of MOS memory cells In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the ... | 05/20/2008 |
| 7368788 | SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter ... | 05/06/2008 |
| 7364276 | Continuous ink jet apparatus with integrated drop action devices and control circuitry A continuous liquid drop emission apparatus is provided. The liquid drop emission apparatus is comprised of a liquid chamber containing a positively pressurized liquid in flow communication with at least one nozzle for emitting a continuous stream of liquid and a je... | 04/29/2008 |
| 7361960 | Semiconductor device and method of manufacturing the same A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the ... | 04/22/2008 |
| 7361578 | Method to form large grain size polysilicon films by nuclei-induced solid phase crystallization A method to enhance grain size in polysilicon films while avoiding formation of hemispherical grains (HSG) is disclosed. The method begins by depositing a first amorphous silicon film, then depositing silicon nuclei, which will act as nucleation sites, on the amorph... | 04/22/2008 |
| 7361961 | Method and apparatus with varying gate oxide thickness An integrated circuit having an enhanced on-off swing for pass gate transistors is provided. The integrated circuit includes a core region that includes core transistors and pass gate transistors. The core transistors have a gate oxide associated with a first thickn... | 04/22/2008 |
| 7358575 | Method of fabricating SRAM device A method of fabricating an SRAM device is provided, by which a junction node area is stably secured in a 1T type SRAM device. The method includes forming first and second conductor patterns on a cell area of a semiconductor substrate and a third conductor pattern on... | 04/15/2008 |
| 7355880 | Soft error resistant memory cell and method of manufacture A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A ... | 04/08/2008 |
| 7348827 | Apparatus and methods for adjusting performance of programmable logic devices A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmab... | 03/25/2008 |
| 7339242 | NAND-type flash memory devices and fabrication methods thereof In an embodiment, a memory device includes a semiconductor substrate having cell active regions and a peripheral active region. Plugs, including bit line contact plugs, a common source line, a peripheral gate interconnection contact plug, and peripheral metal interc... | 03/04/2008 |
