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| Number | Title | Issue Date |
| 8178932 | Semiconductor device having transistors A semiconductor device includes a first transistor having a threshold voltage (Vth) adjusted to a first Vth by a first dopant having a first peak of concentration at a first depth; and a second transistor having the same channel-type as that of the first transistor ... | 05/15/2012 |
| 8174081 | Fully depleted silicon-on-insulator CMOS logic A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without t... | 05/08/2012 |
| 8148785 | Semiconductor device A semiconductor device can output a reference voltage for an arbitrary potential and can detect the voltage of each cell in a battery including multiple cells very precisely. The device includes a depletion-type MOSFET 21 and an enhancement type MOSFET 22 | 04/03/2012 |
| 8143677 | Transistor, a transistor arrangement and method thereof A transistor, transistor arrangement and method thereof are provided. The example method may include determining whether a gate width of the transistor has been adjusted; and adjusting a distance between a higher-concentration impurity-doped region of the transistor... | 03/27/2012 |
| 8129797 | Work function engineering for eDRAM MOSFETs Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantiall... | 03/06/2012 |
| 8129798 | Semiconductor device comprising fully-depleted and partially-depleted FinFETs A semiconductor device includes a circuit comprising a first transistor in a first Fin; a power supply circuit in a second Fin, the power supply circuit comprising a second transistor connected between the circuit and a power supply line; and a substrate contact ele... | 03/06/2012 |
| 8120121 | Semiconductor device A semiconductor device including a first transistor in a substrate, a second transistor in the substrate, and a further device in the substrate. The second transistor and the further device are arranged to operate at a second voltage which is higher than a first vol... | 02/21/2012 |
| 8097923 | Method for fabricating higher quality thicker gate oxide in a non-volatile memory cell and associated circuits A non-volatile memory cell includes a program transistor and a control capacitor. A portion of a substrate associated with the program transistor is exposed to multiple implantations (such as DNW, HiNWell, HiPWell, and P-well implantations). Similarly, a portion of ... | 01/17/2012 |
| 8067807 | Semiconductor integrated circuit device In an LCD driver IC, a high-breakdown-voltage MISFET is mounted together with a typical low-breakdown-voltage MISFET. Because the high-breakdown-voltage MISFET has a gate oxide film thicker than that of the typical MISFET, the electrode of the high-breakdown-voltage... | 11/29/2011 |
| 8063450 | Assembly of nanoscaled field effect transistors The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostr... | 11/22/2011 |
| 8030713 | Semiconductor device A silicon-germanium non-formation region not formed with a silicon germanium layer and a silicon-germanium formation region formed with a silicon germanium layer are provided in a silicon chip, an internal circuit and an input/output buffer are arranged in the silic... | 10/04/2011 |
| 7989898 | Method for fabricating a dual workfunction semiconductor device and the device made thereof A dual workfunction semiconductor device and a device made thereof is disclosed. In one aspect, the device includes a first gate stack in a first region and a second gate stack in a second region. The first gate stack has a first effective workfunction, and the seco... | 08/02/2011 |
| 7989897 | Semiconductor device A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode ... | 08/02/2011 |
| 7973370 | Fully depleted silicon-on-insulator CMOS logic A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without t... | 07/05/2011 |
| 7952150 | Enhancement mode MOSFET and depletion mode FET on a common group III-V substrate The present invention relates to providing an enhancement-mode (e-mode) Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with a complementary depletion-mode (d-mode) FET on a common group III-V substrate. The depletion mode FET may be another MOSFET, a MEt... | 05/31/2011 |
| 7915691 | High density SRAM cell with hybrid devices Hybrid SRAM circuit, hybrid SRAM structures and method of fabricating hybrid SRAMs. The SRAM structures include first and second cross-coupled inverters coupled to first and second pass gate devices. The pull-down devices of the inverters are FinFETs while the pull-... | 03/29/2011 |
| 7911008 | SRAM cell having a rectangular combined active area for planar pass gate and planar pull-down NFETS A planar pass gate NFET is designed with the same width as a planar pull-down NFET. To optimize a beta ratio between the planar pull-down NFET and an adjoined planar pass gate NFET, the threshold voltage of the planar pass gate NFET is increased by providing a diffe... | 03/22/2011 |
| 7906819 | Semiconductor device and method for producing the same The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a p... | 03/15/2011 |
| RE42180 | Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same A semiconductor device includes a semiconductor substrate, an element-isolating region formed in the semiconductor substrate, a real element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer forme... | 03/01/2011 |
| 7888747 | Semiconductor device and method of fabricating the same A semiconductor device includes a semiconductor substrate; a first impurity diffusion suppression layer and a thicker second impurity diffusion suppression layer formed on the semiconductor substrate in first and second isolated transistor regions; first and second ... | 02/15/2011 |
| 7863690 | Semiconductor device A semiconductor device includes a first field effect transistor and a second field effect transistor. The first field effect transistor includes a first gate electrode formed; first impurity diffused areas; and first sidewall portions. The first sidewall portions in... | 01/04/2011 |
| 7851871 | Semiconductor device and method for fabricating the same A high-voltage transistor and a peripheral circuit including a second conductivity type MOSFET are provided together on a first conductivity type semiconductor substrate. The high-voltage transistor includes: a low concentration drain region of a second conductivity... | 12/14/2010 |
| 7843017 | Start-up control device A transistor having a start-up control element is provided. The transistor includes an N-type depletion mode transistor and an N-type enhancement mode transistor. The N-type depletion mode transistor includes a drain for electrically connecting to an external power ... | 11/30/2010 |
| 7834405 | Semiconductor device including I/O oxide and nitrided core oxide on substrate A semiconductor device includes a semiconductor substrate, wherein the semiconductor substrate includes a core area for core circuits and a peripheral area for peripheral circuits. The semiconductor device includes a core oxide on the semiconductor substrate in the ... | 11/16/2010 |
| 7829957 | Semiconductor device and manufacturing method thereof A semiconductor device which includes both an E-FET and a D-FET and can facilitate control of the Vth in an E-FET and suppress a decrease in the Vf, and a manufacturing method of the same are provided. A semiconductor device which includes both an E-FET and a D-FET ... | 11/09/2010 |
| 7781847 | Device patterned with sub-lithographic features with variable widths A method of processing a substrate of a device comprises the as following steps. Form a cap layer over the substrate. Form a dummy layer over the cap layer, the cap layer having a top surface. Etch the dummy layer forming patterned dummy elements of variable widths ... | 08/24/2010 |
| 7772656 | Combination planar FET and FinFET device A semiconductor device. The device including: a planar FET formed in a single crystal-silicon substrate, the FET comprising a first channel region, first and second source drains on opposite sides of the first channel region and a gate, the gate over the channel reg... | 08/10/2010 |
| 7750417 | Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory A non-volatile semiconductor memory includes memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor. ... | 07/06/2010 |
| 7737509 | Semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same... | 06/15/2010 |
| 7728392 | SRAM device structure including same band gap transistors having gate stacks with high-K dielectrics and same work function An SRAM semiconductor device includes: at least a first and a second field effect transistor formed on a same substrate, each of the transistors including a gate stack, each gate stack including a semiconductor layer disposed on a metal layer, the metal layer being ... | 06/01/2010 |
| 7709904 | Thin film transistor substrate and method for manufacturing the same A thin film transistor substrate is provided including a first thin film transistor and a second thin film transistor. The first thin film transistor comprises a first active layer, a first gate insulating film, and a first gate electrode. The second thin film trans... | 05/04/2010 |
| 7598574 | Semiconductor device including a SRAM section and a logic circuit section A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor sub... | 10/06/2009 |
| 7592677 | Over-voltage protected semiconductor device and fabrication In accordance with the principles of the invention, a semiconductor substrate is provided that has a first cell formed thereon. The first cell has first and second terminals or nodes and a control terminal or node and has a characteristic breakdown voltage across th... | 09/22/2009 |
| 7569898 | Semiconductor device and method of manufacturing the same A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region o... | 08/04/2009 |
| 7550809 | Semiconductor integrated circuit device having deposited layer for gate insulation A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transist... | 06/23/2009 |
| 7521765 | Semiconductor device An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also p... | 04/21/2009 |
| RE40579 | Structure for transistor devices in an SRAM cell An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each ... | 11/25/2008 |
| 7443224 | Multi-threshold MIS integrated circuit device and circuit design method thereof On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The ... | 10/28/2008 |
| 7439140 | Formation of standard voltage threshold and low voltage threshold MOSFET devices Wells are formed in a substrate where standard Vt and low Vt devices of both a first and second type are to be fabricated. Wells defining the locations of first type standard Vt devices are masked, and a first voltage threshold implant adjustment is performed within... | 10/21/2008 |
| 7435652 | Integration schemes for fabricating polysilicon gate MOSFET and high-K dielectric metal gate MOSFET Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite diff... | 10/14/2008 |