Class 257/391 - Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations)

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein selected groups of complete IGFETs
No. of patents: 405
Last issue date: 01/31/2012

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Number	Title	Issue Date
8106463	Memory cells for read only memories A ROM memory cell has significantly less total area than previously known ROM memory cells. Instead of using only one layer in the manufacturing process to program the memory cells, at least two layers are used to program the memory cells. This flexibility allows th...	01/31/2012
7999331	Semiconductor device and method of fabricating the same In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an imp...	08/16/2011
7982274	Device comprising doped nano-component A device comprising a doped semiconductor nano-component and a method of forming the device are disclosed. The nano-component is one of a nanotube, nanowire or a nanocrystal film, which may be doped by exposure to an organic amine-containing dopant. Illustrative exa...	07/19/2011
7952149	Anti-halo compensation An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type ...	05/31/2011
7939898	Diffusion variability control and transistor device sizing using threshold voltage implant A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the ope...	05/10/2011
7812408	Integrated circuits with metal-oxide-semiconductor transistors having enhanced gate depletion layers An integrated circuit is provided with groups of transistors that handle different maximum voltage levels. The transistors may be metal-oxide-semiconductor transistors having body, source, drain, and gate terminals. The gate of each transistor may have a gate insula...	10/12/2010
7772655	Semiconductor device and method of fabricating the same In a semiconductor substrate in a first section, a channel region having an impurity concentration peak in an interior of the semiconductor substrate is formed, and in the semiconductor substrate in a second section and a third section, channel regions having an imp...	08/10/2010
7750416	Modifying work function in PMOS devices by counter-doping A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semico...	07/06/2010
7737507	Insulated gate field effect transistors The invention relates to FETs with stripe cells (6). Some of the cells have alternating low and high threshold regions (10, 8) along their length. In a linear operations regime, the low threshold regions conduct preferentially and increase the current ...	06/15/2010
7737506	Semiconductor device and method of manufacturing the same An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in...	06/15/2010
7737508	Non-volatile semiconductor memory device and method of manufacturing the same A non-volatile semiconductor memory device is disclosed, which comprises a memory cell unit including at least one memory cell transistor formed on a semiconductor substrate and having a laminated structure of a charge accumulation layer and a control gate layer, an...	06/15/2010
7732872	Integration scheme for multiple metal gate work function structures A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work func...	06/08/2010
7705406	Transistor array with selected subset having suppressed layout sensitivity of threshold voltage A method for smoothing variations in threshold voltage in an integrated circuit layout. The method begins by identifying recombination surfaces associated with transistors in the layout. Such recombination surfaces are treated to affect the recombination of intersti...	04/27/2010
7602029	Configuration and method of manufacturing the one-time programmable (OTP) memory cells This invention discloses an one time programmable (OTP) memory. The OTP memory includes a first and a second metal oxide semiconductor (MOS) transistors connected in parallel and controlled by a single polysilicon stripe functioning as a gate wherein the OTP memory ...	10/13/2009
7495295	Semiconductor device and method for fabricating the same In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr...	02/24/2009
7442998	Non-volatile memory device A method of fabricating a non-volatile memory is provided. A memory cell array having first memory units and second memory units is formed on a substrate. Then, a source region and a drain region are formed in the substrate on the respective sides of the memory cell...	10/28/2008
RE40532	Non-volatile memory cell and fabrication method Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen th...	10/07/2008
7408230	EEPROM device having first and second doped regions that increase an effective channel length Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side reg...	08/05/2008
7408231	SRAM memory semiconductor integrated circuit device In an integrated circuit device, there are various optimum gate lengths, thickness of gate oxide films, and threshold voltages according to the characteristics of circuits. In a semiconductor integrated circuit device in which the circuits are integrated on the same...	08/05/2008
7391063	Display device A display device has C-MOS p-Si TFTs which enable high integration by reducing spaces for P-MOS TFTs and N-MOS TFTs in a driving circuit or the like thereof. A self-aligned C-MOS process is adopted, which uses a half tone mask as an exposure mask for manufacturing t...	06/24/2008
7382029	Method and apparatus for improving integrated circuit device performance using hybrid crystal orientations A method for implementing a desired offset in device characteristics of an integrated circuit includes forming a first device of a first conductivity type on a first portion of a substrate having a first crystal lattice orientation, and forming a second device of th...	06/03/2008
7375409	Semiconductor device including transistors having different drain breakdown voltages on a single substrate A semiconductor device is provided comprising a supporting substrate, an insulating layer on the substrate, and a first semiconductor layer on the insulating layer. A first high breakdown-voltage transistor is formed in the first semiconductor layer, a second semico...	05/20/2008
7365389	Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory...	04/29/2008
7361932	Semiconductor device and method for fabricating the same A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a...	04/22/2008
7361958	Nonplanar transistors with metal gate electrodes A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first...	04/22/2008
7355256	MOS Devices with different gate lengths and different gate polysilicon grain sizes A semiconductor device 1 according to the present invention includes a semiconductor substrate 5, a first transistor 10 which is formed on the semiconductor substrate 5 and includes a first gate electrode portion 16 constituted by ...	04/08/2008
7352032	Output driver with split pins The drains of the PMOS transistor and the NMOS transistor of a driver are separated and connected to two spaced-apart pins. The spaced-apart pins provide ESD protection to the NMOS transistor, which can be turned on during an ESD event by voltages that propagate thr...	04/01/2008
7339231	Semiconductor device and an integrated circuit card There is provided a technology capable of enhancing reliability in rewrite of storage information in a nonvolatile memory while checking an increase in area of a memory array thereof. With a memory array configuration, individual bit lines are connected to two memor...	03/04/2008
7339239	Vertical NROM NAND flash memory array Memory devices, arrays, and strings are described that facilitate the use of NROM memory cells in NAND architecture memory strings, arrays, and devices. NROM NAND architecture memory embodiments of the present invention include NROM memory cells in high density vert...	03/04/2008
7329929	SRAM cell and method of manufacturing the same Disclosed is a SRAM cell and a method of manufacturing the same. The SRAM cell comprises: a pair of access devices; a pair of pull-up devices; a pair of pull-down devices; and at least one metal plate formed on metal interconnection lines in contact with a substrate...	02/12/2008
7323726	Method and apparatus for coupling to a common line in an array A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopant...	01/29/2008
7323754	Semiconductor device and its manufacture method Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the firs...	01/29/2008
7323424	Semiconductor constructions comprising cerium oxide and titanium oxide The invention includes semiconductor constructions comprising dielectric materials which contain cerium oxide and titanium oxide. The dielectric materials can contain a homogeneous distribution of cerium oxide and titanium oxide, and/or can contain a laminate of cer...	01/29/2008
7312503	Semiconductor memory device including MOS transistors each having a floating gate and a control gate A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge acc...	12/25/2007
7307332	Semiconductor device and method for fabricating the same The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the sidewall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate ele...	12/11/2007
7307296	Flash memory and fabrication method thereof A flash memory comprises a substrate, control gates, doped regions, an isolation layer, isolation structures, floating gates, tunneling dielectric layers and inter-gate dielectric layers. The control gates are arranged over the substrate with a first direction, and ...	12/11/2007
7301208	Semiconductor device and method for fabricating the same A first doped layer of a conductivity type opposite to that of source/drain regions is formed in a semiconductor substrate under a gate electrode. A second doped layer of the conductivity type opposite to that of the source/drain regions is formed in the semiconduct...	11/27/2007
7294903	Transistor assemblies Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ...	11/13/2007
7291880	Transistor assembly Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry are described. In one embodiment, active areas are formed over a substrate, with one of the ...	11/06/2007
7289355	Pre-written volatile memory cell A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 o...	10/30/2007

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Class 257/391 - Selected groups of complete field effect devices having different threshold voltages (e.g., different channel dopant concentrations)