Class 257/390 - Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the integrated circuit contains a
No. of patents: 1042
Last issue date: 05/22/2012

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Number	Title	Issue Date
8183645	Power semiconductor device including gate lead-out electrode Flexibility for the design of the pattern layout of the gate lead-out electrode and the source electrode is enhanced without increasing the chip thickness of the semiconductor device. A semiconductor device includes a cell region where plural transistor cells are ar...	05/22/2012
8138555	Semiconductor device and its manufacturing method An object of the present invention is to provide an active matrix type display unit having a pixel structure in which a pixel electrode formed in a pixel portion, a scanning line (gate line) and a data line are suitably arranged, and high numerical aperture is reali...	03/20/2012
8115259	Three-dimensional memory device A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical chann...	02/14/2012
8093662	Semiconductor memory Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AAi, AAi+1, . . . , AAn, which extend...	01/10/2012
8072034	Array substrate and method of manufacturing the same According to an embodiment of the invention, an array substrate includes a first test line, a second test line, a first source line group, a second source line group, a plurality of gate lines and a switching device. The first test line extends along a first directi...	12/06/2011
8053845	Semiconductor device including dummy gate part and method of fabricating the same In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The ...	11/08/2011
8018007	Selective floating body SRAM cell A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between th...	09/13/2011
8008732	Semiconductor memory and method of manufacturing the same A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active are...	08/30/2011
7994588	Inverted nonvolatile memory device, stack module, and method of fabricating the same Example embodiments provide a nonvolatile memory device that may be integrated through stacking, a stack module, and a method of fabricating the nonvolatile memory device. In the nonvolatile memory device according to example embodiments, at least one bottom gate el...	08/09/2011
7986015	Semiconductor device with STI and method for manufacturing the semiconductor device A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of ...	07/26/2011
7982273	Masking of repeated overlay and alignment marks to allow reuse of photomasks in a vertical structure A monolithic three dimensional semiconductor device structure includes a first layer including a first occurrence of a first reference mark at a first location, and a second layer including a second occurrence of the first reference mark at a second location, wherei...	07/19/2011
7956424	Mirror bit memory device applying a gate voltage alternately to gate A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes: an ONO film including a charge storage layer on a semiconductor substrate; a plurality of bit lines each extending inside the semiconductor substrate; a pl...	06/07/2011
7928516	Semiconductor storage device and manufacturing method thereof A semiconductor storage device include a semiconductor substrate, an insulating layer provided on the semiconductor substrate and having an opening, a semiconductor layer provided on the insulating layer, the semiconductor layer having a recess at a center of a surf...	04/19/2011
7919823	EEPROM array with well contacts A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell ...	04/05/2011
7915689	Thin film transistor, display device including the same and manufacturing method thereof A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconduc...	03/29/2011
7915690	Die rearrangement package structure using layout process to form a compliant configuration A die rearrangement package structure is provided, which includes a die that having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover a die and the active surface being exposed; a p...	03/29/2011
7906818	Memory array with a pair of memory-cell strings to a single conductive pillar Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second string of serially-coupled second memory cells sharing a single conductive pillar which forms a channel for...	03/15/2011
7898039	Non-volatile memory devices including double diffused junction regions A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions exten...	03/01/2011
7893504	Non-volatile semiconductor memory device with contact plug electrically conductive in response to light Disclosed are a non-volatile semiconductor memory device capable of simplifying the complicated structure of a transistor, and a fabrication method for the same. The non-volatile semiconductor memory device includes a semiconductor substrate including a plurality of...	02/22/2011
7884425	Non-volatile memory devices In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlaye...	02/08/2011
7838947	Read-only memory device coded with selectively insulated gate electrodes During fabrication of a mask read-only memory (ROM) device, a dielectric layer is grown on a substrate. Strip-stacked layers are formed on the dielectric layer, with each strip-stacked layer including a polysilicon and a silicon nitride layer. Source/drain regions a...	11/23/2010
7821080	-ary three-dimensional mask-programmable read-only memory N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of...	10/26/2010
7812404	Nonvolatile memory cell comprising a diode and a resistance-switching material In a novel nonvolatile memory cell formed above a substrate, a diode is paired with a reversible resistance-switching material, preferably a metal oxide or nitride such as, for example, NixOy, NbxOy, TixOy	10/12/2010
7812405	Semiconductor device and method of fabricating the same A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lin...	10/12/2010
7812406	Semiconductor device, method for manufacturing semiconductor device, and method for manufacturing semiconductor memory device A method for manufacturing a semiconductor device has forming a first insulating film on a semiconductor substrate, forming an electrode layer on said first insulating film, etching said electrode layer, said first insulating film and said semiconductor substrate of...	10/12/2010
7812407	Memory array structure with strapping cells A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells i...	10/12/2010
7808053	Method, apparatus, and system for flash memory Embodiments of the present invention provide apparatus, methods and systems that include a substrate including a central region and a peripheral region; a plurality of layers above a surface of the substrate, a first plurality of pitch-multiplied spacers on a top su...	10/05/2010
7808054	OTP memory cell, OTP memory, and method of manufacturing OTP memory cell An OTP memory cell according to the present invention includes: a semiconductor substrate including a lower electrode forming region having a lower electrode formed therein, a diffusion layer forming region having a source and a drain formed therein, a first trench-...	10/05/2010
7777281	Non-volatile transistor memory array incorporating read-only elements with single mask set A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width d...	08/17/2010
7772654	Methods of fabricating nonvolatile memory devices Nonvolatile memory devices and methods of fabricating the same are provided. A semiconductor substrate is provided having a cell field region and a high-voltage field region. Device isolation films are provided on the substrate. The device isolation films define act...	08/10/2010
7745884	Nonvolatile semiconductor memory A nonvolatile semiconductor memory of an aspect of the present invention comprises a plurality of memory cell transistors which are connected in series to one another with a first gate spacing, every two adjacent transistors of the memory cell transistors sharing a ...	06/29/2010
7728390	Multi-level interconnection memory device A method for preventing arcing during deep via plasma etching is provided. The method comprises forming a first patterned set of parallel conductive lines over a substrate and forming a plurality of semiconductor pillars on the first patterned set of parallel conduc...	06/01/2010
7728391	Small-pitch three-dimensional mask-programmable memory The present invention discloses a small-pitch three-dimensional mask-programmable memory (SP-3DmM). It is an ultra-low-cost and ultra-high-density semiconductor memory. SP-3DmM comprises a mask-programmable memory level stacked above the substrate. This memory level...	06/01/2010
7692252	EEPROM array with well contacts A semiconductor integrated circuit device includes a cell well, a memory cell array formed on the cell well and having a memory cell area and cell well contact area, first wiring bodies arranged in the memory cell area, and second wiring bodies arranged in the cell ...	04/06/2010
7683435	Misalignment-tolerant multiplexing/demultiplexing architectures This disclosure relates to misalignment-tolerant multiplexing/demultiplexing architectures. One architecture enables communication with a conductive-structure array having a narrow spacing and pitch. Another architecture can comprise address elements having a width ...	03/23/2010
7675123	Printable non-volatile passive memory element and method of making thereof Passive memory devices comprising a support having at least one conductive surface or surface layer and having on at least one side of the support a passive memory element, the passive memory element comprising a first electrode system, an insulating system and a se...	03/09/2010
7675124	Memory array structure with strapping cells A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells i...	03/09/2010
7675125	NAND-type nonvolatile memory device and related method of manufacture In a NAND type nonvolatile memory device, a first insulating layer covers a common drain region formed in a string active region and a peripheral active region. A second insulating layer covers the first insulating layer. A bit line plug penetrates the first and sec...	03/09/2010
7646069	High density integrated read-only memory (ROM) with reduced access time An integrated circuit memory of the read-only memory type includes at least one memory cell. Each memory cell includes a storage transistor realized in a semiconductor substrate and presenting a source connected to a reference potential, a gate connected to an elect...	01/12/2010
7642606	Semiconductor device having non-volatile memory and method of fabricating the same A memory cell of a non-volatile memory device, comprises: a select transistor gate of a select transistor on a substrate, the select transistor gate comprising: a gate dielectric pattern; and a select gate on the gate dielectric pattern; first and second memory cell...	01/05/2010

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Class 257/390 - Matrix or array of field effect transistors (e.g., array of FETs only some of which are completed, or structure for mask programmed read-only memory (ROM))