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| Number | Title | Issue Date |
| 8022483 | Semiconductor and manufacturing method for the same A semiconductor device and a manufacturing method for the same are disclosed. The semiconductor device includes a gate pattern formed at an upper part of the semiconductor substrate to overlap one side of a drift region, and a shallow oxide region disposed adjacent ... | 09/20/2011 |
| 7919822 | Semiconductor device and method for fabricating the same A semiconductor device that suppresses variation and a drop in the breakdown voltage of transistors. In the semiconductor device in which a logic transistor and a high-breakdown-voltage transistor are formed on one Si substrate, an insulating film which has an openi... | 04/05/2011 |
| 7829956 | SRAM semiconductor device with a compressive stress-inducing insulating film and a tensile stress-inducing insulating film Both a compressive-stress-applying insulating film and a tensile-stress-applying insulating film cover an N-type MIS transistor formed at an SRAM access region of a semiconductor substrate. On the other hand, a tensile-stress-applying insulating film covers an N-typ... | 11/09/2010 |
| 7420241 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gat... | 09/02/2008 |
| 7399992 | Device for defeating reverse engineering of integrated circuits by optical means An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device emits extraneous randomized light emis... | 07/15/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7321143 | Ion-sensitive field effect transistor and method for producing an ion-sensitive field effect transistor An ion-sensitive field effect transistor includes a substrate on which there are formed a source region and a drain region. Above a channel region, the ion-sensitive field effect transistor has a gate with a sensitive layer including a metal oxide nitride mixture an... | 01/22/2008 |
| 7315067 | Native high-voltage n-channel LDMOSFET in standard logic CMOS A native high-voltage n-channel LDMOSFET includes a p− doped substrate, a first n+ doped region disposed in the p− doped substrate, a source terminal coupled to the first n+ doped region, an n− well disposed in the substrate, a second n+ doped region disposed ... | 01/01/2008 |
| 7307323 | Structure to use an etch resistant liner on transistor gate structure to achieve high device performance An etch resistant liner covering sidewalls of a transistor gate stack and along a portion of the substrate at a base of the transistor gate stack. The liner prevents silicide formation on the sidewalls of the gate stack, which may produce electrical shorting, and de... | 12/11/2007 |
| 7279757 | Double-sided extended drain field effect transistor A double-sided extended drain field effect transistor that includes a gate terminal overlying a channel region in a substrate. The substrate includes a drain region of a first carrier type that is laterally separated from the channel region by a first RESURF region ... | 10/09/2007 |
| 7268393 | Semiconductor devices and methods of manufacturing the same Semiconductor devices and methods of manufacturing semiconductor devices which achieve higher integration and higher operating speed are provided. A disclosed example semiconductor device includes a semiconductor substrate of a first conductivity type; a gate insula... | 09/11/2007 |
| 7268392 | Trench gate semiconductor device with a reduction in switching loss A semiconductor device comprises: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a trench formed in the second semiconductor region; a thick gate insu... | 09/11/2007 |
| 7253071 | Methods for enhancing the formation of nickel mono-silicide by reducing the formation of nickel di-silicide Methods for reducing stress in silicon to enhance the formation of nickel mono-silicide films formed thereon include a strain compensation source/drain implant process, a silicide formation process on an amorphous silicon layer, a strain compensating buried layer pr... | 08/07/2007 |
| 7253482 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 08/07/2007 |
| 7224037 | Semiconductor integrated circuit device with high and low breakdown-voltage MISFETs Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions o... | 05/29/2007 |
| 7221028 | High voltage transistor and method of manufacturing the same The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the ... | 05/22/2007 |
| 7179537 | Spin-on glass composition and method of forming silicon oxide layer in semiconductor manufacturing process using the same A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing perhydropolysilazane h... | 02/20/2007 |
| 7180129 | Semiconductor device including insulating layer A method of manufacturing an insulating layer that ensures reproducibility across like manufacturing apparatus. The insulating layer is formed on the substrate by (a) flowing an oxidizing gas at an oxidizing gas flow rate, (b) flowing a first carrier gas at a first ... | 02/20/2007 |
| 7176527 | Semiconductor device and method of fabricating same A semiconductor device and a method of fabricating the same suppress a substrate floating effect without causing lowering of a degree of integration. The semiconductor device has a Silicon-On-Insulator structure which includes a semiconductor layer formed on an insu... | 02/13/2007 |
| 7173339 | Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six, etches doped silicon dioxide with selectivity over both undoped silicon... | 02/06/2007 |
| 7160768 | Method of manufacturing electronic device and method of manufacturing semiconductor device The invention provides a semiconductor device, which removes troubles occurring when the parasitic capacitance between layered wiring lines with an interlayer insulating film therebetween is reduced, and have a simple structure and high reliability. The electronic d... | 01/09/2007 |
| 7161210 | Semiconductor device with source and drain regions A semiconductor device is provided with a gate electrode formed over a substrate that has gate oxide films disposed thereon. Source-drain regions of low and high concentration are formed next to the gate electrode. A diffusion region width of the source side of the ... | 01/09/2007 |
| 7157757 | Semiconductor constructions The invention includes semiconductor constructions, methods of forming gatelines, and methods of forming transistor structures. The invention can include, for example, a damascene method of forming a gateline. A thin segment of dielectric material is formed between ... | 01/02/2007 |
| 7119404 | High performance strained channel MOSFETs by coupled stress effects Strained channel transistors including a PMOS and NMOS device pair to improve an NMOS device performance without substantially degrading PMOS device performance and method for forming the same, the method including providing a semiconductor substrate; forming strain... | 10/10/2006 |
| 7101764 | High-voltage transistor and fabrication process A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a ... | 09/05/2006 |
| 7072230 | Method and apparatus for standby power reduction in semiconductor devices A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to ... | 07/04/2006 |
| 7067889 | Method for manufacturing semiconductor integrated circuit device A two-type gate process is suitable for forming a gate insulation film partially formed of a high dielectric film, for example, a titanium oxide film (gate insulation film of the internal circuit) having a relative dielectric constant larger than that of silicon nit... | 06/27/2006 |
| 7060575 | Semiconductor device having transistor and method of manufacturing the same A method of forming self-aligned contact holes exposing source/drain regions in a semiconductor substrate using only etch mask layers is provided. In the method, sacrificial spacers are formed of a material having an excellent etching selectivity to the etch mask la... | 06/13/2006 |
| 7053455 | Semiconductor device and method of manufacturing semiconductor device Disclosed is a semiconductor device comprising a substrate, an insulating film formed above the substrate and containing a metal, Si, N and O, the insulating film containing metal-N bonds larger than the sum total of metal-metal bonds and metal-Si bonds, and an elec... | 05/30/2006 |
| 7038274 | Switching regulator with high-side p-type device A voltage regulator having an input terminal and an output terminal. A PMOS transistor connects the input terminal to an intermediate terminal. The PMOS transistor includes a first gate oxide layer. An LDMOS transistor connects the intermediate terminal to ground. T... | 05/02/2006 |
| 7005705 | MOS transistor on an SOI substrate with a body contact and a gate insulating film with variable thickness It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gat... | 02/28/2006 |
| 6979875 | Reduced surface field technique for semiconductor devices A power device and a method for manufacturing the same are provided. The power device comprises a first conductive semiconductor substrate; a second conductive buried layer formed to a certain depth within the semiconductor substrate; a second conductive epitaxial l... | 12/27/2005 |
| 6943404 | Sonos multi-level memory cell A multi-level memory cell includes a substrate, an insulation layer, a silicon stripe, a first control gate, a second control gate, source/drain regions, silicon oxide/silicon nitride/silicon oxide composite layers. The insulation layer and the silicon stripe are se... | 09/13/2005 |
| 6919606 | Semiconductor device comprising an insulating mask formed on parts of a gate electrode and semiconductor layer crossing an active region A semiconductor device includes a semiconductor layer of a first conductive type formed in an active region, a first gate electrode formed on the semiconductor layer via a gate insulating film in a predetermined pattern, a first insulating mask formed on at least a ... | 07/19/2005 |
| 6919600 | Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact A permanently-ON MOS transistor comprises silicon source and drain regions of a first conductivity type in a silicon well region of a second conductivity type. A silicon contact region of the first conductivity types is buried in the well region, said contact region... | 07/19/2005 |
| 6914295 | Tri-gate devices and methods of fabrication The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite ... | 07/05/2005 |
| 6909145 | Metal spacer gate for CMOS FET A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilico... | 06/21/2005 |
| 6906389 | High-voltage, high-cutoff-frequency electronic MOS device An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a... | 06/14/2005 |
| 6894350 | LDMOS transistor capable of attaining high withstand voltage with low on-resistance and having a structure suitable for incorporation with other MOS transistors A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same s... | 05/17/2005 |
| 6888205 | Metal oxide semiconductor field-effect transistor having a gate oxide layer with portions of different thicknesses and associated methods A metal oxide semiconductor transistor integrated in a wafer of semiconductor material includes a gate structure located on a surface of the wafer and includes a gate oxide layer. The gate oxide layer includes a first portion having a first thickness and a second po... | 05/03/2005 |
