Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8183644 | Metal gate structure of a CMOS semiconductor device The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising a P-active region, an N-active region, and an isolation region interpose... | 05/22/2012 |
| 8143676 | Semiconductor device having a high-dielectric-constant gate insulating film A semiconductor device includes a substrate having first and second regions on a surface thereof, a first conductivity type first MISFET formed in the first region and a second conductivity type second MISFET formed in the second region. The first MISFET includes a ... | 03/27/2012 |
| 7795690 | Thin film transistor substrate and method of fabricating the same The invention relates to a thin film transistor substrate for use in a liquid crystal display device and a method of fabricating the same, and an object is to provide a thin film transistor substrate which can ensure high reliability even though a low resistance met... | 09/14/2010 |
| 7705405 | Methods for the formation of fully silicided metal gates An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. Methods of form... | 04/27/2010 |
| 7498641 | Partial replacement silicide gate A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer.... | 03/03/2009 |
| 7485934 | Integrated semiconductor structure for SRAM cells A semiconductor structure includes a semiconductor substrate having a first device area and a second device area. A gate layer is formed across the first device area and the second device area on the semiconductor substrate, wherein a first portion of the gate layer... | 02/03/2009 |
| 7473975 | Fully silicided metal gate semiconductor device structure A method for forming a semiconductor device structure, comprising the steps of independently forming source/drain surface metal silicide layers and a fully silicided metal gate in a polysilicon gate stack. Specifically, one or more sets of spacer structures are prov... | 01/06/2009 |
| 7465996 | Semiconductor device and method for fabricating the same A semiconductor device includes: a semiconductor substrate divided into a first region and a second region; a first MIS transistor formed in the first region of the semiconductor substrate and including a stack of a first gate insulating film and a fully-silicided f... | 12/16/2008 |
| 7439596 | Transistors for semiconductor device and methods of fabricating the same The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transist... | 10/21/2008 |
| 7432570 | Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111... | 10/07/2008 |
| 7432559 | Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili... | 10/07/2008 |
| 7429770 | Semiconductor device and manufacturing method thereof A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a ... | 09/30/2008 |
| 7419905 | Gate electrodes and the formation thereof A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si... | 09/02/2008 |
| 7405450 | Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is ... | 07/29/2008 |
| 7402875 | Lateral undercut of metal gate in SOI device Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate. ... | 07/22/2008 |
| 7391086 | Conductive contacts and methods for fabricating conductive contacts for elctrochemical planarization of a work piece Conductive contacts and methods for fabricating conductive contacts for electrochemical mechanical planarization are provided. A conductive contact in accordance with an exemplary embodiment of the invention includes, but is not limited to, a first conductive surfac... | 06/24/2008 |
| 7391089 | Semiconductor device and method of manufacturing the same A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film con... | 06/24/2008 |
| 7387956 | Refractory metal-based electrodes for work function setting in semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (1... | 06/17/2008 |
| 7372108 | Semiconductor device and manufacturing method thereof The present invention discloses a semiconductor device and a manufacturing method thereof which improves its characteristics even though it is miniaturized. According to one aspect of the present invention, it is provided a semiconductor device comprising a first se... | 05/13/2008 |
| 7368715 | Semiconductor apparatus and infrared light sensor A semiconductor apparatus includes a pair of first and second field effect transistors formed on a semiconductor substrate. The pair of first and second field effect transistors has the same configurations except for respective gate electrode sections. The gate elec... | 05/06/2008 |
| 7365010 | Semiconductor device having carbon-containing metal silicide layer and method of fabricating the same Methods of fabricating semiconductor devices having a carbon-containing metal silicide layer and semiconductor devices fabricated by the methods are provided. A representative method includes the steps of preparing a semiconductor substrate and forming a gate electr... | 04/29/2008 |
| 7361604 | Method for reducing dimensions between patterns on a hardmask A semiconductor manufacturing method that includes depositing a first layer over a substrate, providing a layer of hardmask over the first layer, patterning and defining the hardmask layer to form at least two hardmask structures, wherein each hardmask structure inc... | 04/22/2008 |
| 7355255 | Nickel silicide including indium and a method of manufacture therefor The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nicke... | 04/08/2008 |
| 7348629 | Metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 03/25/2008 |
| 7335548 | Method of manufacturing metal-oxide-semiconductor transistor A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing mate... | 02/26/2008 |
| 7332439 | Metal gate transistors with epitaxial source and drain regions An MOS transistor formed on a heavily doped substrate is described. Metal gates are used in low temperature processing to prevent doping from the substrate from diffusing into the channel region of the transistor. ... | 02/19/2008 |
| 7326988 | Semiconductor device and method for fabricating the same A metal film formed of a first metal having relatively high oxygen absorption properties on a silicon region, and then depositing a high dielectric constant film formed of an oxide of a second metal having relatively low oxygen absorption properties on the metal fil... | 02/05/2008 |
| 7321154 | Refractory metal-based electrodes for work function setting in semiconductor devices The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (1... | 01/22/2008 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ... | 01/01/2008 |
| 7314814 | Semiconductor devices and methods of fabricating the same Semiconductor devices and methods of fabricating the same are disclosed. A disclosed method comprises: partially forming a first gate stack; partially forming a second gate stack adjacent the first gate stack; forming a first interlayer dielectric; and completing th... | 01/01/2008 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement A high resistor SRAM memory cell to reduce soft error rate includes a first inverter having an output as a first memory node, and a second inverter having an output as a second memory node. The second memory node is coupled to an input of the first inverter through ... | 12/11/2007 |
| 7294878 | Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a semiconductor substrate, an isolation insulation film filled in a plurality of trenches formed in the semiconductor substrate to define a plurality of element formation regions, a floating gate provided on each of the element... | 11/13/2007 |
| 7271446 | Ultra-thin channel device with raised source and drain and solid source extension doping The inventive method for forming thin channel MOSFETS comprises: providing a structure including at least a substrate having a layer of semiconducting material atop an insulating layer and a gate region formed atop the layer of semiconducting material; forming a con... | 09/18/2007 |
| 7271049 | Method of forming self-aligned low-k gate cap A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be signi... | 09/18/2007 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 07/24/2007 |
| 7230286 | Vertical FET with nanowire channels and a silicided bottom contact A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source... | 06/12/2007 |
| 7230304 | Electric contacts and method of manufacturing thereof, and vacuum interrupter and vacuum circuit breaker using thereof An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road... | 06/12/2007 |
| 7208804 | Crystalline or amorphous medium-K gate oxides, Y0and Gd0 A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset of 2 eV or greater. Gate oxi... | 04/24/2007 |
| 7208805 | Structures comprising a layer free of nitrogen between silicon nitride and photoresist The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma... | 04/24/2007 |
| 7205218 | Method including forming gate dielectrics having multiple lanthanide oxide layers A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide, and a method of fabricating such a dielectric film produce a reliable gate dielectric with a equivalent oxide thickness thinner than attainable using SiO2. A g... | 04/17/2007 |
