Quotables
"The Americans have need of the telephone, but we do not. We have plenty of messenger boys."
Sir William Preece, chief engineer, British Post Office ; 1878
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7394095 | Electrode substrate, thin film transistor, display device and their production In the present invention, a lower electrode is utilized as a photomask to form a liquid-repellent region having a generally same pattern shape as that of the lower electrode and a liquid-attracting region having a generally reversed pattern shape on an insulating fi... | 07/01/2008 |
| 7385261 | Extended drain metal oxide semiconductor transistor and manufacturing method thereof A MOS transistor having an extended drain structure and including a semiconductor substrate formed in a well of a first conductivity type. A gate insulating layer is formed on the substrate, a gate electrode is formed on the gate insulating layer, and a source regio... | 06/10/2008 |
| 7365361 | Semiconductor device and method for manufacturing the same The present invention provides a method for manufacturing a semiconductor device, by which a transistor including an active layer, a gate insulating film in contact with the active layer, and a gate electrode overlapping the active layer with the gate insulating fil... | 04/29/2008 |
| 7361580 | Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a gate insulating layer, a gate electrode, an oxide layer, and sidewalls. The gate insulating layer is formed on the substrate. The gate electrode ... | 04/22/2008 |
| 7358122 | High performance FET devices and methods thereof Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 04/15/2008 |
| 7355245 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 04/08/2008 |
| 7348629 | Metal gated ultra short MOSFET devices MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed o... | 03/25/2008 |
| 7332775 | Protruding spacers for self-aligned contacts A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous c... | 02/19/2008 |
| 7323726 | Method and apparatus for coupling to a common line in an array A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopant... | 01/29/2008 |
| 7315082 | Semiconductor device having integrated circuit contact A process for forming vertical contacts in the manufacture of integrated circuits, and devices so manufactured, is disclosed. The process eliminates the need for precise mask alignment and allows the etch of the contact hole to be controlled independent of the etch ... | 01/01/2008 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7276747 | Semiconductor device having screening electrode and method In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a screening electrode spaced apart from a channel region. ... | 10/02/2007 |
| 7268407 | Schottky barrier tunnel single electron transistor and method of manufacturing the same Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of... | 09/11/2007 |
| 7253482 | Structure for reducing overlap capacitance in field effect transistors A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extend... | 08/07/2007 |
| 7221028 | High voltage transistor and method of manufacturing the same The present invention relates to a high voltage transistor and method of manufacturing the same. The high voltage transistor includes: a channel region which is formed in a semiconductor substrate; a gate insulating film which is formed on the channel region of the ... | 05/22/2007 |
| 7220680 | Method for photolithography in semiconductor manufacturing The present disclosure relates generally to the manufacturing of semiconductor devices. In one example, a method for forming a portion of a semiconductor device includes forming a photo sensitive layer over a substrate, developing the photo sensitive layer to expose... | 05/22/2007 |
| 7214994 | Self aligned metal gates on high-k dielectrics A method for forming a transistor including a self aligned metal gate is provided. According to various method embodiments, a high-k gate dielectric is formed on a substrate and a sacrificial carbon gate is formed on the gate dielectric. Sacrificial carbon sidewall ... | 05/08/2007 |
| 7208399 | Transistor with notched gate A transistor having a gate electrode with a T-shaped cross section is fabricated from a single layer of conductive material using an etching process. A two process etch is performed to form side walls having a notched profile. The notches allow source and drain regi... | 04/24/2007 |
| 7176537 | High performance CMOS with metal-gate and Schottky source/drain A semiconductor device having a metal/metal silicide gate and a Schottky source/drain and a method of forming the same are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a metal or metal silicide gate electrode hav... | 02/13/2007 |
| 7157358 | Method for using a wet etch to manufacturing a semiconductor device having a silicided gate electrode and a method for manufacturing an integrated circuit including the same The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing the semiconductor device, among other possible steps, forming a pol... | 01/02/2007 |
| 7129140 | Method of forming polysilicon gate structures with specific edge profiles for optimization of LDD offset spacing Methods of forming MOSFET devices featuring LDD regions offset from the edges of conductive gate structures has been developed. A first embodiment of this invention features the definition of a tapered conductive gate structure with the foot of the tapered structure... | 10/31/2006 |
| 7125787 | Method of manufacturing insulated gate semiconductor device A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus... | 10/24/2006 |
| 7115923 | Imaging with gate controlled charge storage A pixel cell comprises a photo-conversion device for generating charge and a gate controlled charge storage region for storing photo-generated charge under control of a control gate. The charge storage region can be a single CCD stage having a buried channel to obta... | 10/03/2006 |
| 7102155 | Electrode substrate, thin film transistor, display device and their production In the present invention, a lower electrode is utilized as a photomask to form a liquid-repellent region having a generally same pattern shape as that of the lower electrode and a liquid-attracting region having a generally reversed pattern shape on an insulating fi... | 09/05/2006 |
| 7081387 | Damascene gate multi-mesa MOSFET A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-ind... | 07/25/2006 |
| 7064437 | Semiconductor device having aluminum conductors There is provided a semiconductor device having high reliability, high yield, and such a interconnection structure as short hardly occurs. The semiconductor device comprises a semiconductor substrate, metal conductors formed on a side of a main face of the substrate... | 06/20/2006 |
| 7026691 | Minimizing transistor size in integrated circuits A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local inter... | 04/11/2006 |
| 7023059 | Trenches to reduce lateral silicide growth in integrated circuit technology A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicid... | 04/04/2006 |
| 7019363 | MOS transistor with asymmetrical source/drain extensions A method of fabricating an integrated circuit utilizes symmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The... | 03/28/2006 |
| 7015552 | Dual work function semiconductor structure with borderless contact and method of fabricating the same A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to ... | 03/21/2006 |
| 6958500 | Semiconductor device having low resistivity source and drain electrodes A dummy gate crossing an active area having ends in contact with an isolation area is formed. A low area lower than a dummy gate is formed in the isolation area. Side walls are formed in the active area except the dummy gate. A semiconductor film having the same hei... | 10/25/2005 |
| 6958279 | Method for manufacturing semiconductor device A gate insulator film and a gate electrode are formed on a semiconductor substrate, and then a layered stack of a SiO2 film and a SiN film is formed on the entire surface. Subsequently, sidewalls made of polysilicon film are formed adjacent to the gate el... | 10/25/2005 |
| 6927461 | Semiconductor device having shared contact and fabrication method thereof Semiconductor devices and methods of fabrication. A device includes a semiconductor substrate, a gate electrode insulated from the semiconductor substrate by a gate insulation layer, LDD-type source/drain regions formed at both sides of the gate electrode, an interl... | 08/09/2005 |
| 6921951 | Thin film transistor and pixel structure thereof A thin film transistor and a pixel structure with the same are disclosed. The thin film transistor includes a gate electrode with at least one notch, a gate dielectric layer, a source region, a drain region, and a channel layer. The gate electrode is on a substrate.... | 07/26/2005 |
| 6909186 | High performance FET devices and methods therefor Structure and methods of fabrication are disclosed for an enhanced FET devices in which dopant impurities are prevented from diffusing through the gate insulator. The structure comprises a Si:C, or SiGe:C, layer which is sandwiched between the gate insulator and a l... | 06/21/2005 |
| 6909145 | Metal spacer gate for CMOS FET A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilico... | 06/21/2005 |
| 6897534 | Semiconductor device having gate electrode of stacked structure including polysilicon layer and metal layer and method of manufacturing the same The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of th... | 05/24/2005 |
| 6894350 | LDMOS transistor capable of attaining high withstand voltage with low on-resistance and having a structure suitable for incorporation with other MOS transistors A semiconductor device, methods for manufacturing the semiconductor device, and an integrated circuit including the semiconductor device are disclosed. The semiconductor device includes an LDMOS transistor and a MOS transistor, both formed simultaneously on a same s... | 05/17/2005 |
| 6888198 | Straddled gate FDSOI device A straddled gate device, and a method of producing such device, formed on a semiconductor-on-insulator (SOI) substrate having active regions defined by isolation regions and an insulator layer. The device includes a first gate defining a first channel region interpo... | 05/03/2005 |
| 6885072 | Nonvolatile memory with undercut trapping structure The present invention discloses a nonvolatile memory with undercut trapping structure, the nonvolatile memory comprising a semiconductor substrate. A gate oxide is formed on the semiconductor substrate. A gate structure is formed on the gate oxide, wherein the gate ... | 04/26/2005 |
