Class 257/386 - With means to reduce parasitic capacitance

Subclass of Class 257 - Active solid-state devices (e.g., transistors, solid-state diodes)
Definition: Subject matter wherein the device contains means to reduce
No. of patents: 178
Last issue date: 05/29/2012

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Number	Title	Issue Date
8188548	Device and method for reducing a voltage dependent capacitive coupling A device comprises a first means for separating a conductive layer from a semiconductor substrate and a second means for reducing a voltage dependent capacitive coupling between the conductive layer and the semiconductor substrate. ...	05/29/2012
8102010	Apparatus for reducing parasitic capacitance in a semiconductor device A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semicond...	01/24/2012
8008731	IGFET device having a RF capability An IGFET device includes: —a semiconductor body (2) having a major surface, —a source region (3) of first conductivity type abutting the surface, —a drain region (6,7) of the first conductivity-type abutting the surface and spaced from the...	08/30/2011
7843016	Asymmetric field effect transistor structure and method Disclosed are embodiments for a design structure of an asymmetric field effect transistor structure and a method of forming the structure in which both series resistance in the source region (Rs) and gate to drain capacitance (Cgd) are reduced ...	11/30/2010
7667275	Using oxynitride spacer to reduce parasitic capacitance in CMOS devices A complementary metal oxide semiconductor (CMOS) device has a substrate 100, a gate structure 108 disposed atop the substrate, and spacers 250, deposited on opposite sides of the gate structure 108 to govern formation of deep source drain...	02/23/2010
7569897	Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sectio...	08/04/2009
7545007	MOS varactor with segmented gate doping A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one conta...	06/09/2009
7420260	Power semiconductor device for suppressing substrate recirculation current and method of fabricating power semiconductor device A power semiconductor device has a first region in which a transistor is formed, a third region in which a control element is formed, and a second region for separating the first region and the third region. The power semiconductor device includes a substrate of a f...	09/02/2008
7420241	Semiconductor memory device and method of manufacturing the same A semiconductor memory device includes a memory cell which includes a first gate insulation film provided on the semiconductor substrate; a floating gate electrode provided on the first gate insulation film; a second gate insulation film provided on the floating gat...	09/02/2008
7335956	Capacitor device with vertically arranged capacitor regions of various kinds A capacitor device selectively combines MOM, MIM and varactor regions in the same layout area of an IC. Two or more types of capacitor regions arranged vertically on a substrate to form the capacitor device. This increase the capacitance per unit of the capacitor de...	02/26/2008
7335947	Angled implant for shorter trench emitter An insulated gate trench type semiconductor device having L-shaped diffused regions, each diffused region having a vertically oriented portion and a horizontally oriented portion extending laterally from the vertically oriented portion, and a method for manufacturin...	02/26/2008
7288817	Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co...	10/30/2007
7288786	Integrated circuit configuration with analysis protection and method for producing the configuration During the creation of wiring plans for logic modules, the regions which are left free of interconnects by synthesis methods in upper metal planes are filled to a maximum degree with further interconnects. These interconnects serve to protect the integrated circuit....	10/30/2007
7282772	Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sectio...	10/16/2007
7273788	Ultra-thin semiconductors bonded on glass substrates A method for forming a semiconductor on insulator structure includes providing a glass substrate, providing a semiconductor wafer, and performing a bonding cut process on the semiconductor wafer and the glass substrate to provide a thin semiconductor layer bonded to...	09/25/2007
7262428	Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the...	08/28/2007
7233515	Integrated memory arrangement based on resistive memory cells and production method An integrated memory arrangement based on resistive memory cells that can be changed over between a first state of high electrical resistance and a second state of low electrical resistance, each memory cell having an electrical additional capacitance that increases...	06/19/2007
7208805	Structures comprising a layer free of nitrogen between silicon nitride and photoresist The invention includes a semiconductor processing method. A first material comprising silicon and nitrogen is formed. A second material is formed over the first material, and the second material comprises silicon and less nitrogen, by atom percent, than the first ma...	04/24/2007
7205618	Semiconductor device and method for manufacturing the same A semiconductor device includes a silicon substrate, a channel region formed in a surface of the silicon substrate, a gate insulating film formed on the channel region, a gate electrode formed on the gate insulating film, first gate side walls formed on the gate ins...	04/17/2007
7190043	Techniques to create low K ILD for beol One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l...	03/13/2007
7183193	Integrated device technology using a buried power buss for major device and circuit advantages A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidiz...	02/27/2007
7180071	Integrated circuit having radiation sensor arrangement Integrated circuit including a circuit unit having predefined functionality and a radiation sensor arrangement connected indirectly to the circuit unit. The radiation sensor arrangement has at least one radiation-sensitive element that has at least one circuit prope...	02/20/2007
7166882	Semiconductor device and method for fabricating the same The semiconductor device comprises: an insulation film 72 formed over a silicon substrate 10, an insulation film 78 formed on the insulation film 72 and having opening 82, and conductor 84 formed at least in the opening 8...	01/23/2007
7161199	Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive...	01/09/2007
7157387	Techniques to create low K ILD for BEOL One aspect of the present subject matter relates to a method for forming an interlayer dielectric (ILD). In various embodiments of the method, an insulator layer is formed, at least one trench is formed in the insulator layer, and a metal layer is formed in the at l...	01/02/2007
7153753	Strained Si/SiGe/SOI islands and processes of making same A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A the...	12/26/2006
7119393	Transistor having fully-depleted junctions to reduce capacitance and increase radiation immunity in an integrated circuit A floating-gate transistor for an integrated circuit is formed on a p-type substrate. An n-type region is disposed over the p-type substrate. A p-type region is disposed over the n-type region. Spaced apart n-type source and drain regions are disposed in the p-type ...	10/10/2006
7115957	Semiconductor raised source-drain structure A transistor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a...	10/03/2006
7112537	Method of fabricating interconnection structure of semiconductor device A method of fabricating an interconnection structure of a semiconductor device includes the steps of successively depositing an etch-stop layer and an intermetal insulating layer on a semiconductor substrate, forming a sacrificial insulating layer on the intermetal ...	09/26/2006
7061029	High-voltage device structure A high-voltage device structure disposed in a substrate of a first conductivity type includes a first well and a second well each of a second conductivity type, a source diffusion region and a drain diffusion region each of a first length located in the first well a...	06/13/2006
7058922	Semiconductor integrated circuit and method of manufacturing the same A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply...	06/06/2006
7045873	Dynamic threshold voltage MOSFET on SOI Provision of a body control contact adjacent a transistor and between the transistor and a contact to the substrate or well in which the transistor is formed allows connection and disconnection of the substrate of the transistor to and from a zero (ground) or substa...	05/16/2006
7041575	Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi...	05/09/2006
7034347	Charge detecting device There is provided a charge detecting device that can convert an accumulated charge to a voltage at a low voltage and a high efficiency, and has a large dynamic range of an output voltage and satisfactory linearity of a conversion efficiency. The charge detecting dev...	04/25/2006
7023051	Localized strained semiconductor on insulator One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth withi...	04/04/2006
7023059	Trenches to reduce lateral silicide growth in integrated circuit technology A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicid...	04/04/2006
7008854	Silicon oxycarbide substrates for bonded silicon on insulator A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to...	03/07/2006
6995434	Semiconductor device and method of fabricating the same A semiconductor device capable of suppressing increase of the capacitance while suppressing a thin-line effect of a silicide film is obtained. This semiconductor device comprises a first silicon layer formed on a semiconductor substrate through a gate insulator film...	02/07/2006
6992355	Semiconductor-on-insulator constructions The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is fo...	01/31/2006
6951621	Method for forming a product sensor, and a product sensor The invention relates to a method for forming a product sensor, and a product sensor. The product sensor is formed on a substrate and provided with at least one electric circuit comprising at least one capacitor and at least one coil. At least part of the electric c...	10/04/2005

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Class 257/386 - With means to reduce parasitic capacitance