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| Number | Title | Issue Date |
| 7728389 | Semiconductor device and fabrication method for the semiconductor device A semiconductor device and a fabrication method for the semiconductor device which can remove the sacrifice layer deposited on the semiconductor device surface in a short time and whose manufacturing yield can be improved are provided. The semiconductor device and t... | 06/01/2010 |
| 7528451 | CMOS gate conductor having cross-diffusion barrier A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFE... | 05/05/2009 |
| 7427796 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source... | 09/23/2008 |
| 7382028 | Method for forming silicide and semiconductor device formed thereby A method for forming silicide and a semiconductor device formed thereby. A Si-containing polycrystalline region is converted to an amorphous region, and annealed to form a regrown polycrystalline region having an increased grain size. A silicide layer is formed by r... | 06/03/2008 |
| 7345350 | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias A method for forming a conductive via in a semiconductor component is disclosed. The method includes providing a substrate having a first surface and an opposing, second surface. At least one hole is formed in the substrate extending between the first surface and th... | 03/18/2008 |
| 7300851 | Method of fabricating a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 11/27/2007 |
| 7288817 | Reverse metal process for creating a metal silicide transistor gate structure The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate co... | 10/30/2007 |
| 7268052 | Method for reducing soft error rates of memory cells In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical ju... | 09/11/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7236389 | Cross-point RRAM memory array having low bit line crosstalk A cross-point RRAM memory array includes a word line array having an array of substantially parallel word lines therein and a bit line array having an array of substantially parallel bit lines therein, wherein said bit lines are substantially perpendicular to said w... | 06/26/2007 |
| 7230301 | Single-crystal silicon semiconductor structure A resistor, a transistor, and a capacitor can be fabricated on a semiconductor wafer in a process that forms an isolated single-crystal region with precise dimensions. The isolated single-crystal region, in turn, defines the body of the resistor, the gate of the tra... | 06/12/2007 |
| 7199433 | Method of manufacturing semiconductor integrated circuit device having capacitor element In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) ... | 04/03/2007 |
| 7195995 | Method of manufacturing a multilayered doped conductor for a contact in an integrated circuit device A method of manufacturing a memory device addressing reliability and refresh characteristics through the use of a multilayered doped conductor, and a method making is described. The multilayered doped conductor creates a high dopant concentration in the active area ... | 03/27/2007 |
| 7196382 | Transistor, method for producing an integrated circuit and a method of producing a metal silicide layer The invention relates to a method for the selective silicidation of contact areas that allow the production of highly integrated circuits, preferably in a SMOS or BiCMOS process. To this end, a metal oxide layer (14) that contains for example praseodymium oxi... | 03/27/2007 |
| 7190036 | Transistor mobility improvement by adjusting stress in shallow trench isolation A method of improving transistor carrier mobility by adjusting stress through recessing shallow trench isolation is presented. A trench is formed in a substrate. The trench is filled with a dielectric. A CMOS transistor is formed adjacent to the trench. A silicide l... | 03/13/2007 |
| 7190035 | Semiconductor device having elevated source/drain on source region and drain region A semiconductor device disclosed herein comprises: an element isolation insulator which is formed on the surface side of a semiconductor substrate to provide electrical insulation from other elements, a height of a surface of the element isolation insulator being eq... | 03/13/2007 |
| 7176534 | Low resistance T-gate MOSFET device using a damascene gate process and an innovative oxide removal etch The present invention provides a method for fabricating low-resistance, sub-0.1 μm channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate s... | 02/13/2007 |
| 7145196 | Asymmetric field effect transistor A field effect transistor includes a channel region under a gate stack formed on a semiconductor structure. The field effect transistor also includes a drain region formed with a first dopant doping a first side of the channel region, and includes a source region fo... | 12/05/2006 |
| 7125787 | Method of manufacturing insulated gate semiconductor device A gate electrode includes a first polysilicon film remaining on a first oxide film, a part of a second polysilicon layer 8 superimposed on the polysilicon layer, and a part of the second polysilicon layer partially extending over second gate oxide films. Thus... | 10/24/2006 |
| 7122470 | Semiconductor device with a CMOS transistor A semiconductor device having a gate electrode free from increasing of resistance of the gate electrode, from decreasing of capacitance of the insulation film due to depletion, and from penetrating of impurity. The semiconductor device includes a silicon layer, a ga... | 10/17/2006 |
| 7112855 | Low ohmic layout technique for MOS transistors The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect... | 09/26/2006 |
| 7112501 | Method of fabrication a silicon-on-insulator device with a channel stop A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral par... | 09/26/2006 |
| 7102201 | Strained semiconductor device structures Semiconductor fabrication methods and structures, devices and integrated circuits characterized by enhanced operating performance. The structures generally include first and second source/drain regions formed in a body of a semiconductor material and a channel regio... | 09/05/2006 |
| 7091113 | Methods of forming semiconductor constructions The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. Th... | 08/15/2006 |
| 7081656 | CMOS constructions The invention includes methods of forming circuit devices. A metal-containing material comprising a thickness of no more than 20 Å (or alternatively comprising a thickness resulting from no more than 70 ALD cycles) is formed between conductively-doped silicon and ... | 07/25/2006 |
| 7075159 | Horizontal MOS transistor This invention provides a horizontal MOS transistor capable of improving current drivability and reducing ON resistance by optimizing the gate wiring structure and the disposition structure of source/drain layers. First gate wirings are disposed in the X direction a... | 07/11/2006 |
| 7067888 | Semiconductor device and a method of manufacturing the same Semiconductor regions for the suppression of short channel effects are not provided for a pMIS and an nMIS that constitute an inverter circuit of an input first stage of an I/O buffer circuit, whereas semiconductor regions for the suppression of short channel effect... | 06/27/2006 |
| 7064034 | Technique for fabricating logic elements using multiple gate layers Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and mem... | 06/20/2006 |
| 7027322 | EPIR device and semiconductor devices utilizing the same There is provided an EPIR device which is excellent in mass productivity and high in practical utility. The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various su... | 04/11/2006 |
| 7009279 | Semiconductor device configured for suppressed germanium diffusion from a germanium-doped regions and a method for fabrication thereof In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has... | 03/07/2006 |
| 7008849 | Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direct... | 03/07/2006 |
| 6977205 | Method for manufacturing SOI LOCOS MOSFET with metal oxide film or impurity-implanted field oxide This invention provides a semiconductor device with an element isolation implemented by a method of manufacturing a semiconductor device comprising the steps of: forming a pad oxide film 140 and a nitride film 150 sequentially on a silicon layer 130... | 12/20/2005 |
| 6967382 | Integrated circuit devices including raised source/drain structures having different heights Integrated circuit devices including raised source/drain structures having different heights are disclosed. An integrated circuit device can include a first raised source/drain structure having a first height above a substrate in a first region of the integrated cir... | 11/22/2005 |
| 6965137 | Multi-layer conductive memory device A multilayered conductive memory device capable of storing information individually or as part of an array of memory devices is provided. Boundary control issues at the interface between layers of the device due to the use of incompatible materials can be avoided by... | 11/15/2005 |
| 6955992 | One mask PT/PCMO/PT stack etching process for RRAM applications A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the h... | 10/18/2005 |
| 6953974 | EEPROM device and method for providing lower programming voltage An improved EEPROM device and method for providing a lower device programming voltage is disclosed. An exemplary EEPROM device is configured with a modified drawing layer comprising one or more serrated elements configured underneath a tunneling region of the EEPROM... | 10/11/2005 |
| 6940172 | Chemical vapor deposition of titanium A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second prec... | 09/06/2005 |
| 6940143 | Semiconductor thin-film manufacturing method, semiconductor device manufacturing method, semiconductor device, integrated circuit, electro-optical device, and electronic appliance According to the semiconductor thin-film and semiconductor device manufacturing method of the present invention, an insulating film having a through-hole between two layers of silicon film is provided, the silicon film is partially melted by irradiating a laser ther... | 09/06/2005 |
| 6924560 | Compact SRAM cell with FinFET A method and system is disclosed for an SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type. The cell has a first device of the first type constructed as a part of a first FinFET having one... | 08/02/2005 |
| 6914309 | Semiconductor device with double sidewall spacer and layered contact A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silic... | 07/05/2005 |
