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| Number | Title | Issue Date |
| 8183643 | Semiconductor device having silicide layer completely occupied amorphous layer formed in the substrate and an interface junction of (111) silicon plane A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers... | 05/22/2012 |
| 8120120 | Embedded silicon germanium source drain structure with reduced silicide encroachment and contact resistance and enhanced channel mobility Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first port... | 02/21/2012 |
| 8093661 | Integrated circuit device with single crystal silicon on silicide and manufacturing method A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a sec... | 01/10/2012 |
| 8063449 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and... | 11/22/2011 |
| 8044470 | Semiconductor device and method of fabricating the same Provided is a semiconductor device including a transistor that has a silicide layer formed over a semiconductor substrate. The gate electrode of each transistor is composed of a polysilicon electrode and the silicide layer formed thereon. Each transistor further has... | 10/25/2011 |
| 8022482 | Device configuration of asymmetrical DMOSFET with schottky barrier source A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surro... | 09/20/2011 |
| 8008730 | Semiconductor device, and manufacturing method thereof To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like ... | 08/30/2011 |
| 7982272 | Thin-film semiconductor device and method for manufacturing the same A thin-film semiconductor device including a transparent insulating substrate, an island semiconductor layer formed on the transparent insulating substrate and including a source region containing a first-conductivity-type impurity and a drain region containing a fi... | 07/19/2011 |
| 7911007 | Semiconductor device and method of manufacturing the same A semiconductor device including a silicon substrate and a field effect transistor including a gate insulating film on the silicon substrate, a gate electrode on the gate insulating film, and source/drain regions formed in the substrate on opposite sides of the gate... | 03/22/2011 |
| 7906817 | High compressive stress carbon liners for MOS devices Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor st... | 03/15/2011 |
| 7902612 | Semiconductor device and method of manufacturing the same It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impu... | 03/08/2011 |
| 7843015 | Multi-silicide system in integrated circuit technology An integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. A sidewall spacer is formed around the gate and a source/drain junction is formed in the semiconductor substrate using the sid... | 11/30/2010 |
| 7834404 | Semiconductor device A method of manufacturing a semiconductor device according to the present invention includes the steps of introducing first impurities of a first conductivity type into a main surface of a semiconductor substrate 1 to form a first impurity region, introducing... | 11/16/2010 |
| 7791146 | Semiconductor device including field effect transistor and method of forming the same A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped w... | 09/07/2010 |
| 7786538 | Semiconductor device having a nickel silicide layer on a single crystal silicon layer A semiconductor device includes: a first MOSFET including: first source and drain regions formed at a distance from each other in a first semiconductor region; a first insulating film formed on the first semiconductor region between the first source region and the f... | 08/31/2010 |
| 7786537 | Semiconductor device and method for manufacturing same A semiconductor device includes a silicon substrate; a P channel type field effect transistor including a first gate insulating film on the substrate, a first gate electrode on the first gate insulating film and a first source/drain region; and an N channel type fie... | 08/31/2010 |
| 7768074 | Dual salicide integration for salicide through trench contacts and structures formed thereby Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an NMOS silicide on an NMOS source/drain contact area, forming a first contact metal on the NMOS silicide, polishing the first contact metal to exp... | 08/03/2010 |
| 7759742 | Metal oxide semiconductor transistor A metal oxide semiconductor (MOS) transistor is disclosed. The MOS transistor includes: a semiconductor substrate; a gate disposed on the semiconductor substrate, wherein the gate comprises two sidewalls; a spacer formed on the sidewalls of the gate; a source/drain ... | 07/20/2010 |
| 7714395 | Static random access memory and fabricating method thereof A static random access memory at least includes: pluralities of transistors disposed on a substrate, each transistor at least includes a gate, a gate dielectric layer, a source doped region and a drain doped region, in which some of the source doped regions are used... | 05/11/2010 |
| 7701017 | MOS semiconductor device and method of fabricating the same A MOS semiconductor device includes a substrate having a first region with a Si(110) surface and a second region with a Si(100) surface, a p-channel MOSFET formed in the first region, and an n-channel MOSFET formed in the second region. The p-channel MOSFET includin... | 04/20/2010 |
| 7687866 | Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a semiconductor layer formed partially on a semiconductor substrate by epitaxial growth, an embedded oxide film embedded between the semiconductor substrate and the semiconductor layer, first and second gate electrodes disposed on sid... | 03/30/2010 |
| 7683434 | Preventing cavitation in high aspect ratio dielectric regions of semiconductor device Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures... | 03/23/2010 |
| 7655987 | Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an u... | 02/02/2010 |
| 7652336 | Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming at least one isolation structure within the semiconductor wafer, and... | 01/26/2010 |
| 7633127 | Silicide gate transistors and method of manufacture A method in which a gate and raised source/drain (S/D) regions are fully silicided in separate steps to avoid degrading the resistance or junction leakage is described. A gate dielectric layer, gate, and spacers are formed over a semiconductor layer that is preferab... | 12/15/2009 |
| 7608898 | One transistor DRAM cell structure A one-transistor dynamic random access memory (DRAM) cell includes a transistor which has a first source/drain region, a second source/drain region, a body region between the first and second source/drain regions, and a gate over the body region. The first source/dr... | 10/27/2009 |
| 7550808 | Fully siliciding regions to improve performance Structures and related methods including fully silicided regions are disclosed. In one embodiment, a structure includes a substrate; a partially silicided region located in an active region of an integrated circuit formed on the substrate; a fully silicided region l... | 06/23/2009 |
| 7504698 | Semiconductor device and manufacturing method thereof A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconduct... | 03/17/2009 |
| 7495293 | Semiconductor device and method for manufacturing the same A semiconductor device includes a silicon region including Si, and a silicide film provided on the silicon region, the silicide film comprising a compound of Si with Ni, Co, Pd, or Pt and including Er. ... | 02/24/2009 |
| 7479682 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 01/20/2009 |
| 7459756 | Method for forming a device having multiple silicide types Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the... | 12/02/2008 |
| 7439593 | Semiconductor device having silicide formed with blocking insulation layer Some embodiments include an isolation layer defining an active region of a substrate, a gate pattern formed on the active region, and source/drain regions formed in the active region. Sidewall spacers are formed on sidewalls of the gate pattern, and a blocking insul... | 10/21/2008 |
| 7439596 | Transistors for semiconductor device and methods of fabricating the same The present invention discloses a transistor for a semiconductor device capable of preventing the generation of a depletion capacitance in a gate pattern due to the diffusion of impurity ions. The present invention also discloses a method of fabricating the transist... | 10/21/2008 |
| 7429770 | Semiconductor device and manufacturing method thereof A technique capable of reducing threshold voltage and reducing high-temperature heat treatment after forming a gate electrode is provided. An n-type MIS transistor or a p-type MIS transistor is formed on an active region isolated by an element isolation region of a ... | 09/30/2008 |
| 7427796 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source... | 09/23/2008 |
| 7411258 | Cobalt disilicide structure A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of c... | 08/12/2008 |
| 7411254 | Semiconductor substrate The invention includes methods of forming conductive metal silicides by reaction of metal with silicon. In one implementation, such a method includes providing a semiconductor substrate comprising an exposed elemental silicon containing surface. At least one of a cr... | 08/12/2008 |
| 7405447 | Silicon rich barrier layers for integrated circuit devices Semiconductor devices and memory cells are formed using silicon rich barrier layers to prevent diffusion of dopants from differently doped polysilicon films to overlying conductive layers or to substrates. A polycilicide gate electrode structure may be formed using ... | 07/29/2008 |
| 7405449 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including f... | 07/29/2008 |
| 7391089 | Semiconductor device and method of manufacturing the same A semiconductor device which includes a field effect transistor having a gate electrode on the upper side of a semiconductor substrate, with a gate insulation film therebetween, wherein at least the gate insulation film side of the gate electrode includes a film con... | 06/24/2008 |