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Actor Marlon Brando has four patents, all named "Drumhead tensioning device and method."
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| Number | Title | Issue Date |
| 8138554 | Semiconductor device with local interconnects A semiconductor device with local interconnects is provided. The semiconductor device comprises a first gate line structure and a second gate line structure disposed on a substrate and substantially collinear. A first pair of source/drain regions is formed in the su... | 03/20/2012 |
| 8120119 | Stressed barrier plug slot contact structure for transistor performance enhancement A method for forming a slot contact structure for transistor performance enhancement. A contact opening is formed to expose a contact region, and a slot contact is disposed within the contact opening in order to induce a stress on an adjacent channel region. In an e... | 02/21/2012 |
| 7999330 | Dynamic random access memory device and electronic systems The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalu... | 08/16/2011 |
| 7649232 | P-channel MOS transistor, semiconductor integrated circuit device and fabrication process thereof A p-channel MOS transistor includes source and drain regions of p-type formed in a silicon substrate at respective lateral sides of a gate electrode wherein each of the source and drain regions of p-type includes any of a metal film region and a metal compound film ... | 01/19/2010 |
| 7554162 | Thin film transistor substrate with low reflectance upper electrode A thin film transistor substrate includes an upper electrode for electrically connecting a transparent picture element electrode to the thin film transistor. The upper electrode includes at least a first metal layer and a second metal layer formed on the first metal... | 06/30/2009 |
| 7432560 | Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insul... | 10/07/2008 |
| 7411258 | Cobalt disilicide structure A structure relating to removal of an oxide of titanium generated as a byproduct of a process that forms cobalt disilicide within an insulated-gate field effect transistor (FET). The structure may comprise a layer of cobalt disilicide that is substantially free of c... | 08/12/2008 |
| 7405449 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including f... | 07/29/2008 |
| 7391086 | Conductive contacts and methods for fabricating conductive contacts for elctrochemical planarization of a work piece Conductive contacts and methods for fabricating conductive contacts for electrochemical mechanical planarization are provided. A conductive contact in accordance with an exemplary embodiment of the invention includes, but is not limited to, a first conductive surfac... | 06/24/2008 |
| 7385260 | Semiconductor device having silicide thin film and method of forming the same The present invention provides a semiconductor device having a silicide thin film and method of forming the same. A semiconductor device comprises a gate insulation layer formed on an active region of a semiconductor substrate. A gate electrode is formed on the gate... | 06/10/2008 |
| 7368792 | MOS transistor with elevated source/drain structure In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is fo... | 05/06/2008 |
| 7364995 | Method of forming reduced short channel field effect transistor A method for manufacturing a semiconductor device capable of reducing a short channel effect, whereby the semiconductor device includes a pair of impurity regions for a source and a drain formed on a semiconductor substrate, a gate having a gate electrode used to co... | 04/29/2008 |
| 7348599 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 03/25/2008 |
| 7335967 | Semiconductor device A semiconductor device is provided that includes: a base insulating film; a metal thin-film resistor that is provided on the base insulating film; a lower-layer insulating film that is formed under the base insulating film; and a wiring pattern that is formed on the... | 02/26/2008 |
| 7314789 | Structure and method to generate local mechanical gate stress for MOSFET channel mobility modification A semiconductor structure and method that is capable of generating a local mechanical gate stress for channel mobility modification are provided. The semiconductor structure includes at least one NFET and at least one PFET on a surface of a semiconductor substrate. ... | 01/01/2008 |
| 7312125 | Fully depleted strained semiconductor on insulator transistor and method of making the same An integrated circuit includes multiple layers. A semiconductor-on-insulator (SOI) wafer can be used to house transistors. Two substrates or wafers can be bonded to form the multiple layers. A strained semiconductor layer can be between a silicon germanium layer and... | 12/25/2007 |
| 7307322 | Ultra-uniform silicide system in integrated circuit technology A structure of an integrated circuit is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over a gate dielectric on the semiconductor substrate. Source/drain junctions are formed in the semiconductor substrate. Ultra-uniform su... | 12/11/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7294581 | Method for fabricating silicon nitride spacer structures Embodiments of methods for fabricating a spacer structure on a semiconductor substrate are provided herein. In one embodiment, a method for fabricating a spacer structure on a semiconductor substrate includes providing a substrate containing a base structure over wh... | 11/13/2007 |
| 7279414 | Method of forming interconnect structure with interlayer dielectric The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance of oxidation of the upper surface of a metallic interconnect is achieved according to the present inventi... | 10/09/2007 |
| 7276767 | Thin film resistor device and a method of manufacture therefor The present invention provides a thin film resistor and method of manufacture therefor. The thin film resistor comprises a resistive layer located on a first dielectric layer, first and second contact pads located on the resistive layer, and a second dielectric laye... | 10/02/2007 |
| 7273804 | Internally reinforced bond pads Disclosed is a reinforced bond pad structure having nonplanar dielectric structures and a metallic bond layer conformally formed over the nonplanar dielectric structures. The nonplanar dielectric structures are substantially reproduced in the metallic bond layer so ... | 09/25/2007 |
| 7271455 | Formation of fully silicided metal gate using dual self-aligned silicide process An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of for... | 09/18/2007 |
| 7262987 | SRAM cell using tunnel current loading devices An SRAM cell with gate tunneling load devices. The SRAM cell uses PFET wordline transistors and NFET cross-coupled transistors. The PFET wordline transistors are fully conductive during read operations, thus a full voltage level is passed through the PFET to the hig... | 08/28/2007 |
| 7262456 | Bit line structure and production method thereof The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled wi... | 08/28/2007 |
| 7259432 | Semiconductor device for reducing parasitic capacitance produced in the vicinity of a transistor located within the semiconductor device A semiconductor device includes: a gate electrode formed on a substrate; impurity regions formed in the substrate and to both sides of the gate electrode; a first interlayer insulating film formed to cover the gate electrode; and a second interlayer insulating film ... | 08/21/2007 |
| 7250661 | Semiconductor memory device with plural source/drain regions A semiconductor memory device includes first and second source/drain regions, and first and second semiconductor regions. The first source/drain region of a first conductive type is formed in a first well region of a second conductive type for a pair of first MIS-ty... | 07/31/2007 |
| 7242063 | Symmetric non-intrusive and covert technique to render a transistor permanently non-operable A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when sta... | 07/10/2007 |
| 7230286 | Vertical FET with nanowire channels and a silicided bottom contact A vertical FET structure with nanowire forming the FET channels is disclosed. The nanowires are formed over a conductive silicide layer. The nanowires are gated by a surrounding gate. Top and bottom insulator plugs function as gate spacers and reduce the gate-source... | 06/12/2007 |
| 7230304 | Electric contacts and method of manufacturing thereof, and vacuum interrupter and vacuum circuit breaker using thereof An electric contact member which is excellent in voltage-proof performance and melt-resistant performance and excellent in mass productivity, and a method of manufacturing thereof, and a vacuum interrupter, a vacuum circuit breaker and a load-break switch for a road... | 06/12/2007 |
| 7226859 | Method of forming different silicide portions on different silicon-containing regions in a semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 06/05/2007 |
| 7217657 | Semiconductor device having different metal silicide portions and method for fabricating the semiconductor device A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a... | 05/15/2007 |
| 7217954 | Silicon carbide semiconductor device and method for fabricating the same An inventive semiconductor device is provided with: a silicon carbide substrate 1; an n-type high resistance layer 2; well regions 3 provided in a surface region of the high resistance layer 2; a p+ contact region 4 prov... | 05/15/2007 |
| 7217977 | Covert transformation of transistor properties as a circuit protection method A technique for and structures for camouflaging an integrated circuit structure. The technique includes the use of a light density dopant (LDD) region of opposite type from the active regions resulting in a transistor that is always off when standard voltages are ap... | 05/15/2007 |
| 7211200 | Manufacture and cleaning of a semiconductor Metal nitride and metal oxynitride extrusions often form on metal silicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etc... | 05/01/2007 |
| 7208760 | Active matrix electroluminescent display devices, and their manufacture Physical barriers (210) are present between neighbouring pixels (200) on a circuit substrate (100) of an active-matrix electroluminescent display device, particularly with LEDs (25) of organic semi conductor materials. The invention forms... | 04/24/2007 |
| 7208762 | Semiconductor device and manufacturing method thereof A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, a GOLD structure or an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel portion is connected to the pixel TFT through a hole bored in at l... | 04/24/2007 |
| 7199011 | Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer... | 04/03/2007 |
| 7196000 | Method for manufacturing a wafer level chip scale package A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an emb... | 03/27/2007 |
| 7190010 | Semiconductor device A semiconductor device includes a semiconductor substrate, a T-shaped gate electrode, a moisture-proof insulating film, and an interlayer dielectric film. The T-shaped gate electrode has a leg portion joined to the semiconductor substrate and an overhanging head por... | 03/13/2007 |
