Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8178931 | Bridge for semiconductor internal node A method and apparatus for forming connections within a semiconductor device is disclosed. The semiconductor device incorporates a contact bridge between transistor contacts in close proximity. The contact bridge comprises a plurality of metal pillars each having a ... | 05/15/2012 |
| 8102009 | Integrated circuit eliminating source/drain junction spiking An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor ... | 01/24/2012 |
| 8008729 | Integrated circuit with a contact structure including a portion arranged in a cavity of a semiconductor structure An integrated circuit includes a contact structure with a buried first and a protruding second portion. The buried first portion is arranged in a cavity formed in a semiconductor structure and is in direct contact with the semiconductor structure. The protruding sec... | 08/30/2011 |
| 7968949 | Contact forming method and related semiconductor device Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the stru... | 06/28/2011 |
| 7960797 | Semiconductor devices including fine pitch arrays with staggered contacts A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one or both of misalignment during fabrication of the contacts and contact resistance between sections of the... | 06/14/2011 |
| 7939897 | Method of forming a low resistance semiconductor contact and structure therefor In one embodiment, silicide layers are formed on two oppositely doped adjacent semiconductor regions. A conductor material is formed electrically contacting both of the two silicides. ... | 05/10/2011 |
| 7915688 | Semiconductor device with MISFET A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes whic... | 03/29/2011 |
| 7911005 | Dram having deeper source drain region than that of an logic region A semiconductor device having a DRAM region and a logic region embedded together therein, including a first transistor formed in a DRAM region, and having a first source/drain region containing arsenic and phosphorus as impurities; and a second transistor formed in ... | 03/22/2011 |
| 7911006 | Structure and fabrication method for capacitors integratible with vertical replacement gate transistors A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a fir... | 03/22/2011 |
| 7859063 | Semiconductor device using SOI-substrate According to a feature of the present invention, a semiconductor device includes a SOI substrate, including a semiconductor substrate; an insulating layer formed on the semiconductor substrate and a silicon layer formed on the insulating layer. A drain region and a ... | 12/28/2010 |
| 7843014 | Small size transistor semiconductor device capable of withstanding high voltage In one embodiment of the present invention, a high withstand voltage transistor is disclosed having small sizes including an element isolating region. The semiconductor device is provided with the element isolating region formed on a semiconductor substrate; an acti... | 11/30/2010 |
| 7759741 | Method and apparatus for forming nickel silicide with low defect density in FET devices A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in... | 07/20/2010 |
| 7750415 | Structure and method for making high density MOSFET circuits with different height contact lines Embodiments herein present a structure, method, etc. for making high density MOSFET circuits with different height contact lines. The MOSFET circuits include a contact line, a first gate layer situated proximate the contact line, and at least one subsequent gate lay... | 07/06/2010 |
| 7741682 | Semiconductor integrated circuit device including a silicon layer formed on a diffusion layer A semiconductor integrated circuit device having a pair of adjacent MOS transistors and a contact plug 33, buried into a contact hole formed by a self-aligned contact process using a silicon nitride film as an etching stopper and electrically connected to dif... | 06/22/2010 |
| 7732871 | MOS transistor and manufacturing method thereof Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, a... | 06/08/2010 |
| 7719062 | Tuned tensile stress low resistivity slot contact structure for n-type transistor performance enhancement A method for forming a slot contact structure for n-type transistor performance enhancement. A slot contact opening is formed to expose a contact region, and a barrier plug is disposed within a portion of the slot contact opening in order to induce a tensile stress ... | 05/18/2010 |
| 7709903 | Contact barrier structure and manufacturing methods A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal lay... | 05/04/2010 |
| 7696583 | Thin film transistor and method of fabricating the same A thin film transistor and a method of fabricating the same capable of reducing stress of a substrate caused by a metal layer of the drain and source electrodes, the thin film transistor including a substrate; a semiconductor layer disposed on the substrate and incl... | 04/13/2010 |
| 7667274 | Semiconductor device and method of manufacturing the same A semiconductor device is disclosed, which comprises a silicon substrate, a complementary MISFET circuit, an insulation film formed on the silicon substrate, a first contact hole formed in the insulation film, a first metal silicide layer formed on the bottom of the... | 02/23/2010 |
| 7655986 | Systems and methods for reducing contact to gate shorts A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed on a substrate, a contact is formed on the gate and the substrate, and an insulator is formed between the... | 02/02/2010 |
| 7633126 | Semiconductor device having a shared contact and method of fabricating the same In view of micronizing semiconductor device and of suppressing current leakage in a shared contact allowing contact between a gate electrode and an impurity-diffused region, a semiconductor device 100 includes a first gate electrode 108, a fourth sourc... | 12/15/2009 |
| 7569896 | Transistors with stressed channels A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/d... | 08/04/2009 |
| 7564104 | Low ohmic layout technique for MOS transistors A transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one... | 07/21/2009 |
| 7560783 | Metal-semiconductor contact, semiconductor component, integrated circuit arrangement and method The present invention relates to a metal-semiconductor contact comprising a semiconductor layer and comprising a metallization applied to the semiconductor layer, a high dopant concentration being introduced into the semiconductor layer such that a non-reactive meta... | 07/14/2009 |
| 7550807 | Semiconductor memory In the non-volatile semiconductor memory in which an N-type source diffusion layer and an N-type drain diffusion layer are formed on a P-type well formed on a substrate: the source diffusion layer has a protrusion portion and a depressed portion on a cross section t... | 06/23/2009 |
| 7545006 | CMOS devices with graded silicide regions A semiconductor device includes a semiconductor substrate, a gate stack overlying the semiconductor substrate, a spacer on a sidewall of the gate stack, a lightly doped source/drain (LDD) region adjacent the gate stack, a deep source/drain region adjoining the LDD r... | 06/09/2009 |
| 7538398 | System and method for forming a semiconductor device source/drain contact The present invention discloses a semiconductor source/drain contact structure, which comprises a substrate, a source/drain region disposed in the substrate, at least one non-silicided conductive layer including a barrier layer disposed over and in contact with the ... | 05/26/2009 |
| 7514756 | Semiconductor device with MISFET A semiconductor device includes a substrate, a semiconductor region provided in the substrate, a group of transistors including a plurality of MIS transistors and provided in the semiconductor region, the MIS transistors including a plurality of gate electrodes whic... | 04/07/2009 |
| 7511349 | Contact or via hole structure with enlarged bottom critical dimension An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the diel... | 03/31/2009 |
| 7498640 | Self-aligned silicide process for silicon sidewall source and drain contacts and structure formed thereby A method (and structure formed thereby) of forming a metal silicide contact on a non-planar silicon containing region having controlled consumption of the silicon containing region, includes forming a blanket metal layer over the silicon containing region, forming a... | 03/03/2009 |
| 7446379 | Transistor with dopant-bearing metal in source and drain A transistor and method of manufacturing thereof. A gate dielectric and gate are formed over a workpiece, and the source and drain regions of a transistor are recessed. The recesses are filled with a dopant-bearing metal, and a low-temperature anneal process is used... | 11/04/2008 |
| 7439566 | Semiconductor memory device having metal-insulator transition film resistor A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a f... | 10/21/2008 |
| 7439571 | Method for fabricating metal gate structures Methods of forming a microelectronic structure are described. Those methods comprise providing a substrate comprising source/drain and gate regions, wherein the gate region comprises a metal layer disposed on a gate dielectric layer, and then laser annealing the sub... | 10/21/2008 |
| 7436017 | Semiconductor integrated circuit using a selective disposable spacer Methods of manufacturing a semiconductor integrated circuit using selective disposable spacer technology and semiconductor integrated circuits manufactured thereby: The method includes forming a plurality of gate patterns on a semiconductor substrate. Gap regions be... | 10/14/2008 |
| 7432560 | Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insul... | 10/07/2008 |
| 7411284 | Accessible electronic storage apparatus A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semicon... | 08/12/2008 |
| 7405449 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate, and a MOS transistor provided on the semiconductor substrate and having a channel type of a first conductivity, the MOS transistor comprising a semiconductor region of the first conductivity type including f... | 07/29/2008 |
| 7402872 | Method for forming an integrated circuit A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in... | 07/22/2008 |
| 7397131 | Self-aligned semiconductor contact structures A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer tha... | 07/08/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
