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...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 7919821 | Method and integrated circuits capable of saving layout areas An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section.... | 04/05/2011 |
| 7786536 | Semiconductor device and method for fabricating the same In a semiconductor device, a first p-type MIS transistor includes: a first gate insulating film formed on a first active region; a first gate electrode formed on the first gate insulating film; a first side-wall insulating film; a first p-type source/drain region; a... | 08/31/2010 |
| 7750414 | Structure and method for reducing threshold voltage variation A structure comprises at least one transistor on a substrate, an insulator layer over the transistor, and an ion stopping layer over the insulator layer. The ion stopping layer comprises a portion of the insulator layer that is damaged and has either argon ion damag... | 07/06/2010 |
| 7642605 | Semiconductor device A semiconductor device includes a glass substrate having a main surface, a polysilicon film formed on the main surface, having a channel region formed and having a source region and a drain region formed on opposing sides of the channel region, a gate insulating fil... | 01/05/2010 |
| 7411822 | Nonvolatile memory cell arrangement Memory transistors are arranged in a plurality of rows and columns. A first source/drain terminal of each memory transistor of a first column is connected to an electrically conductive conductor track in a first metallization plane, and a first source/drain terminal... | 08/12/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7288453 | Method of fabricating analog capacitor using post-treatment technique There is provided a method of fabricating an analog capacitor using a post-treatment technique. The method includes forming a lower insulating layer on a semiconductor substrate. A bottom electrode is formed on the lower insulating layer, and a capacitor dielectric ... | 10/30/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7208369 | Dual poly layer and method of manufacture Semiconductor devices having a dual polysilicon electrode and a method of manufacturing are provided. The semiconductor devices include a first polysilicon layer deposited on a second polysilicon layer. Each polysilicon layer may be doped individually. The method al... | 04/24/2007 |
| 7176533 | Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug... | 02/13/2007 |
| 7160781 | Transistor device and methods of manufacture thereof Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the sec... | 01/09/2007 |
| 7067439 | ALD metal oxide deposition process using direct oxidation Methods of forming metal compounds such as metal oxides or metal nitrides by sequentially introducing and then reacting metal organic compounds with ozone or with oxygen radicals or nitrogen radicals formed in a remote plasma chamber. The metal compounds have surpri... | 06/27/2006 |
| 7064398 | Semiconductor memory device In a full CMOS SRAM having a lateral type cell (memory cell having three partitioned wells arranged side by side in a word line extending direction and longer in the word line direction than in the bit line direction) including first and second driver MOS transistor... | 06/20/2006 |
| 7049665 | Method of manufacturing a dual gate semiconductor device with a poly-metal electrode In order to realize a dual gate CMOS semiconductor device with little leakage of boron that makes it possible to divisionally doping a p-type impurity and an n-type impurity into a polycrystalline silicon layer with one mask, a gate electrode has a high melting poin... | 05/23/2006 |
| 7023080 | Semiconductor integrated circuit with dummy patterns A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an ... | 04/04/2006 |
| 6953974 | EEPROM device and method for providing lower programming voltage An improved EEPROM device and method for providing a lower device programming voltage is disclosed. An exemplary EEPROM device is configured with a modified drawing layer comprising one or more serrated elements configured underneath a tunneling region of the EEPROM... | 10/11/2005 |
| 6924560 | Compact SRAM cell with FinFET A method and system is disclosed for an SRAM device cell having at least one device of a first semiconductor type and at lease one device of a second semiconductor type. The cell has a first device of the first type constructed as a part of a first FinFET having one... | 08/02/2005 |
| 6921962 | Integrated circuit having a thin film resistor located within a multilevel dielectric between an upper and lower metal interconnect layer A thin film resistor (60) is contained between two metal interconnect layers (40, 100) of an integrated circuit. Contact may be made to the resistor (60) through vias (95) from the metal layer (100) above the resistor (60) t... | 07/26/2005 |
| 6911384 | Gate structure with independently tailored vertical doping profile A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second co... | 06/28/2005 |
| 6894365 | Semiconductor device having an integral resistance element A resistance element of a semiconductor device includes a first resistance pattern and a second resistance pattern formed adjacent to the first resistance pattern at a lower level, wherein the second resistance pattern is defined by the first resistance pattern in a... | 05/17/2005 |
| 6885070 | Semiconductor memory device and fabrication method thereof In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gat... | 04/26/2005 |
| 6882015 | Intralevel decoupling capacitor, method of manufacture and testing circuit of the same A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single inte... | 04/19/2005 |
| 6870231 | Layouts for CMOS SRAM cells and devices SRAM cells and devices are provided. The SRAM cells may share connections with neighboring cells, including ground, power supply voltage and/or bit line connections. SRAM cells and devices are also provided that include first and second active regions disposed at a ... | 03/22/2005 |
| 6867462 | Semiconductor device using an SOI substrate and having a trench isolation and method for fabricating the same A trench isolation region separating active regions in which MISFETs are formed includes: side insulating films covering the sides of a trench; polycrystalline semiconductor layers of a first conductivity type covering the respective sides of the side insulating fil... | 03/15/2005 |
| 6822288 | Trench MOSFET device with polycrystalline silicon source contact structure A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carr... | 11/23/2004 |
| 6815839 | Soft error resistant semiconductor memory device The semiconductor memory device includes two PMOS transistors that make the SRAM memory cell. The gate insulating films of these PMOS transistors are formed using a material that has a high permittivity. As a result, the capacitance of memory nodes is increased, and... | 11/09/2004 |
| 6812515 | Polysilicon layers structure and method of forming same A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysili... | 11/02/2004 |
| 6797575 | Method for forming a polycide structure in a semiconductor device A method for preventing void formation in a polycide structure includes sequentially depositing a gate oxide film, a polysilicon film doped with impurities, a seed film having a sufficient amount of silicon for reacting with an overlaying tungsten layer, a tungsten ... | 09/28/2004 |
| 6770939 | Thermal processing for three dimensional circuits An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing op... | 08/03/2004 |
| 6753556 | Silicate gate dielectric A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing g... | 06/22/2004 |
| 6747307 | Combined transistor-capacitor structure in deep sub-micron CMOS for power amplifiers A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of elect... | 06/08/2004 |
| 6717233 | Method for fabricating resistors within semiconductor integrated circuit devices A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first conta... | 04/06/2004 |
| 6686645 | Fuse and fuse window structure A fuse structure. A first dielectric layer is formed on a substrate, a first conductive layer is formed on part of the first dielectric layer, a second dielectric layer is formed on part of the first dielectric layer and part of the first conductive layer... | 02/03/2004 |
| 6674132 | Memory cell and production method A memory cell, which is isolated from other memory cells by STI trenches, each includes an ONO layer structure between a gate electrode and a channel region formed in a semiconductor body. The gate electrode is a component of a strip-shaped word line. Sou... | 01/06/2004 |
| 6674108 | Gate length control for semiconductor chip design A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of... | 01/06/2004 |
| 6657265 | Semiconductor device and its manufacturing method A semiconductor device includes metal silicide films formed on the surface of a source-drain region and of a gate electrode. On the metal silicide films, impurity regions are formed of a conductivity type opposite to the conductivity type of the source-dr... | 12/02/2003 |
| 6635937 | Semiconductor integrated circuit device To improve performance, a capacitor is provided between storage nodes of an SRAM and a device having an analog capacitor on a single substrate, a plug is formed in a silicon oxide film on a pair of n channel type MISFETs in a memory cell forming area, and... | 10/21/2003 |
| 6610569 | Semiconductor device and process of producing the same The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of produci... | 08/26/2003 |
| 6600210 | Semiconductor device and method of manufacturing the same A semiconductor device is provided, which is provided with a high resistance to surge currents. The semiconductor device comprises three N+ diffusion layers 4a, 4b, and 4c in a region surrounded by an element-separating insulating film 3a. The ... | 07/29/2003 |
| 6586808 | Semiconductor device having multi-work function gate electrode and multi-segment gate dielectric A MOSFET and methods of fabrication. The MOSFET includes a gate having a center gate electrode portion being spaced from the layer of semiconductor material by a center gate dielectric. The gate also includes a lateral gate electrode portion adjacent each... | 07/01/2003 |
