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| Number | Title | Issue Date |
| 8154085 | Nonvolatile semiconductor memory has resistors including electrode layer formed on low resistance layer adjacent to mask film A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a ... | 04/10/2012 |
| 8154086 | Semiconductor surround gate SRAM storage device It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS t... | 04/10/2012 |
| 8026556 | Adjustible resistor for use in a resistive divider circuit and method for manufacturing A method of manufacturing a resistive divider circuit, includes providing a silicon body having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem supporting a relatively wider silicon platform. A silicidat... | 09/27/2011 |
| 7595535 | Resistor of semiconductor device and method for fabricating the same A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer... | 09/29/2009 |
| 7586162 | High-value integrated resistor and method of making A high value resistive device in an integrated circuit is disclosed, including a pair of substantially similar resistor segments each having an elongated semiconductor channel of e.g. silicon, lightly doped as would be appropriate for a low-threshold depletion mode ... | 09/08/2009 |
| 7538397 | Semiconductor device and method for fabricating the same A semiconductor device includes a resistor element covered by a silicon oxide film. In the semiconductor device, with respective gate electrodes of MIS transistors and impurity doped layers, i.e., non-silicide regions exposed, thermal treatment for activating an imp... | 05/26/2009 |
| 7485933 | Semiconductor integrated circuit device having polycrystalline silicon resistor circuit A semiconductor device has a first insulating film formed on a semiconductor substrate and resistors disposed on the first insulating film. Each of the resistors is formed of a polycrystalline silicon film having a low concentration impurity region and high concentr... | 02/03/2009 |
| 7439147 | Resistor of semiconductor device and method for fabricating the same A resistor for a semiconductor device is provided. The resistor can include a first polysilicon layer formed on a semiconductor substrate; an insulating layer formed on regions of the first polysilicon layer; a second polysilicon layer formed on the insulating layer... | 10/21/2008 |
| 7411284 | Accessible electronic storage apparatus A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semicon... | 08/12/2008 |
| 7405470 | Adaptable electronic storage apparatus A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semicon... | 07/29/2008 |
| 7365397 | Semiconductor device The semiconductor device comprises a resistance element 26 formed of polysilicon film formed on a silicon substrate 10, which includes a resistor part 26a having a resistance value set at a prescribed value, contact parts 26b | 04/29/2008 |
| 7361960 | Semiconductor device and method of manufacturing the same A first insulator film and a first polysilicon film are formed on first and second element regions of a semiconductor substrate. The first insulator film and first polysilicon film are removed from the second element region. A second insulator film is formed on the ... | 04/22/2008 |
| 7351627 | Method of manufacturing semiconductor device using gate-through ion implantation Disclosed herein is a method of manufacturing a semiconductor device via gate-through ion implantation, comprising forming a gate stack on a semiconductor substrate and performing ion implantation for control of the threshold voltage and junction ion implantation fo... | 04/01/2008 |
| 7342285 | Method of fabricating semiconductor devices A method of fabricating a semiconductor device is disclosed. First, a substrate is provided. The substrate includes at least a transistor area having a gate structure thereon, a capacitor area having a first electrode thereon and a resistor area having a second elec... | 03/11/2008 |
| 7323751 | Thin film resistor integration in a dual damascene structure A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over t... | 01/29/2008 |
| 7319254 | Semiconductor memory device having resistor and method of fabricating the same A semiconductor device having resistors in a peripheral area and fabrication method thereof are provided. A mold layer is formed on a semiconductor substrate. The mold layer is patterned to form first molding holes and a second molding hole in the mold layer. A stor... | 01/15/2008 |
| 7317239 | Method for manufacturing a resistor A method of manufacturing a resistor is provided. At first, a semiconductor layer including at least a high resistance region and a low resistance region is formed on a substrate. Following that, a first ion implantation process is performed to the entire surface of... | 01/08/2008 |
| 7271454 | Semiconductor memory device and method of manufacturing the same A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor ar... | 09/18/2007 |
| 7247511 | Thin film phase-change memory A memory cell comprises a chalcogenide random access memory (CRAM) cell and a CMOS circuit. The CMOS circuit accesses the CRAM cell. The CRAM cell has a cross-sectional area that is determined by a thin film process (e.g., a chalcogenide deposition thin film process... | 07/24/2007 |
| 7244995 | Scrambling method to reduce wordline coupling noise A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a ... | 07/17/2007 |
| 7238582 | Semiconductor device and process of producing the same The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same... | 07/03/2007 |
| 7233518 | Radiation-hardened SRAM cell with write error protection A method and system is disclosed for preventing write errors in a Single Event Upset (SEU) hardened static random access memory (SRAM) cell. A compensating element has been connected to a feedback path of the SRAM cell. The compensating element operates to cancel ou... | 06/19/2007 |
| 7217981 | Tunable temperature coefficient of resistance resistors and method of fabricating same Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the sa... | 05/15/2007 |
| 7218315 | Display device, electronic appliance and camera A display device, which defines an attached state or a removed state with respect to an electronic appliance, includes a display section, a driver for driving the display section, a transceiver for transmitting or receiving a signal to/from the electronic appliance,... | 05/15/2007 |
| 7214990 | Memory cell with reduced soft error rate The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transi... | 05/08/2007 |
| 7208814 | Resistive device and method for its production A resistive device includes a resistive region of a semiconductor material that includes a first region and a second region, wherein the first region has a higher dopant concentration than the second region, and wherein a resistance-determining width of a current pa... | 04/24/2007 |
| 7196377 | MOS type semiconductor device having electrostatic discharge protection arrangement In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. ... | 03/27/2007 |
| 7195966 | Methods of fabricating semiconductor devices including polysilicon resistors and related devices Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating ... | 03/27/2007 |
| 7190609 | Semiconductor memory device with memory cells operated by boosted voltage A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory c... | 03/13/2007 |
| 7183626 | Passivation structure with voltage equalizing loops A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop... | 02/27/2007 |
| 7176530 | Configuration and fabrication of semiconductor structure having n-channel channel-junction field-effect transistor A semiconductor technology combines a normally off n-channel channel-junction insulated-gate field-effect transistor (“IGFET”) (104) and an n-channel surface-channel IGFET (100 or 160) to reduce low-frequency 1/f noise. The channel-junction ... | 02/13/2007 |
| 7148556 | High performance diode-implanted voltage-controlled poly resistors for mixed-signal and RF applications A p-type polysilicon resistor formed in the inter-level dielectric layer contains an implanted diode. A positive voltage applied to the diode modulates the depletion region of the diode and changes the absolute resistance of the p-type polysilicon resistor. This mod... | 12/12/2006 |
| 7141511 | Method and apparatus for fabricating a memory device with a dielectric etch stop layer The present technique relates to a method and apparatus to provide a dielectric etch stop layer that prevents shorts for a buried digit layer as an interconnect. In a memory device, such as DRAM or SRAM, various layers are deposited to form structures, such as PMOS ... | 11/28/2006 |
| 7112855 | Low ohmic layout technique for MOS transistors The disclosure relates to a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect... | 09/26/2006 |
| 7113246 | Image display having internal wiring with multi-layer structure and manufacturing method thereof having particular wiring connection An image display in which a resistance value of internal wiring for inputting a signal and a power supply to a driving IC COG-packaged on an insulating substrate composing a display panel is reduced without enlarging external size of the display panel, and a method ... | 09/26/2006 |
| 7109566 | Semiconductor device with resistor pattern and method of fabricating the same Disclosed is a semiconductor device with a resistor pattern and methods of fabricating the same. Embodiments of the present invention provide a method of fabricating a resistor pattern having high sheet resistance by using a polycide layer for a gate electrode in a ... | 09/19/2006 |
| 7110281 | Memory cells utilizing metal-to-metal capacitors to reduce susceptibility to single event upsets Structures and methods of adding metal-to-metal capacitors to static memory cells to reduce susceptibility to SEUs. The addition of metal-to-metal capacitors is particularly suited to programmable logic devices (PLDs), because of the relatively large area required t... | 09/19/2006 |
| 7105912 | Resistor structure and method for manufacturing the same A resistor structure includes a substrate, a semiconductor layer positioned on the substrate, a salicide block positioned on portions of the surface of the semiconductor layer, and at least a salicide layer positioned on the portions of the surface of the semiconduc... | 09/12/2006 |
| 7084478 | Load resistor with dummy contact substantially free of charge build up during etching process A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the co... | 08/01/2006 |
| 7078786 | Composite series resistor having reduced temperature sensitivity in an IC chip According to one exemplary embodiment, an integrated circuit chip comprises an oxide region. The integrated circuit chip further comprises a poly resistor having a first terminal and second terminal, where the poly resistor is situated over the oxide region. Accordi... | 07/18/2006 |
