Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 8173993 | Gate-all-around nanowire tunnel field effect transistors A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure a... | 05/08/2012 |
| 8173992 | Transistor or triode structure with tunneling effect and insulating nanochannel A microelectronic device is provided with at least one transistor or triode with Fowler-Nordheim tunneling current modulation, and supported on a substrate. The triode or the transistor includes at least one first block forming a cathode and at least one second bloc... | 05/08/2012 |
| 7655942 | Fiber incorporating quantum dots as programmable dopants A programmable dopant fiber includes a plurality of quantum structures formed on a fiber-shaped substrate, wherein the substrate includes one or more energy-carrying control paths, which pass energy to quantum structures. Quantum structures may include quantum dot p... | 02/02/2010 |
| 7449713 | Semiconductor memory device A semiconductor memory device includes a semiconductor substrate, a semiconductor layer, a source/drain layer, first and second insulating films, and first and second gate electrodes. The semiconductor layer of one conductivity type is formed on a principal surface ... | 11/11/2008 |
| 7439089 | Method of fabricating array substrate having color filter on thin film transistor structure In a liquid crystal display device substrate, an insulating layer covers a thin film transistor. Another insulating layer covers a black matrix, which is formed on the insulating layer and covers the thin film transistor, a gate line, and a data line except a portio... | 10/21/2008 |
| 7400017 | Reverse conducting semiconductor device and a fabrication method thereof To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type ba... | 07/15/2008 |
| 7378328 | Method of fabricating memory device utilizing carbon nanotubes A fast, reliable, highly integrated memory device formed of a carbon nanotube memory device and a method for forming the same, in which the carbon nanotube memory device includes a substrate, a source electrode, a drain electrode, a carbon nanotube having high elect... | 05/27/2008 |
| 7311947 | Laser assisted material deposition A method of forming a film on a substrate includes activating a gas precursor to form a material on the substrate by irradiating the gas precursor with electromagnetic energy at a frequency tuned to an absorption frequency of the gas precursor. ... | 12/25/2007 |
| 7288473 | Metal layer in semiconductor device and method of forming the same Canting or falling of an upper metal line may be prevented by improving adhesion between an insulation layer and a metal layer. A method for forming a semiconductor which improves adhesion between an insulation layer and a metal layer includes: preparing a substrate... | 10/30/2007 |
| 7250648 | Ferroelectric rare-earth manganese-titanium oxides Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices. ... | 07/31/2007 |
| 7196351 | Forming phase change memories Phase change memories may exhibit improved properties and lower cost in some cases by forming the phase change material layers in a planar configuration. A heater may be provided below the phase change material layers to appropriately heat the material to induce the... | 03/27/2007 |
| 7190037 | Integrated transistor devices A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulat... | 03/13/2007 |
| 7187587 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 03/06/2007 |
| 7183568 | Piezoelectric array with strain dependant conducting elements and method therefor A structure (and method) for a piezoelectric device, including a layer of piezoelectric material. A nanotube structure is mounted such that a change of shape of the piezoelectric material causes a change in a stress in the nanotube structure. ... | 02/27/2007 |
| 7161838 | Thin film transistor memory device A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffus... | 01/09/2007 |
| 7157731 | Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of ... | 01/02/2007 |
| 7112841 | Graded composition metal oxide tunnel barrier interpoly insulators Structures and methods for programmable array type logic and/or memory devices with graded composition metal oxide tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include a floating gate transistor. The float... | 09/26/2006 |
| 7112494 | Write once read only memory employing charge trapping in insulators Structures and methods for write once read only memory employing charge trapping in insulators are provided. The write once read only memory cell includes a metal oxide semiconductor field effect transistor having a first source/drain region, a second source/drain r... | 09/26/2006 |
| 7087954 | In service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu... | 08/08/2006 |
| 7075829 | Programmable memory address and decode circuits with low tunnel barrier interpoly insulators Structures and methods for programmable memory address and decode circuits with low tunnel barrier interpoly insulators are provided. The decoder for a memory device includes a number of address lines and a number of output lines wherein the address lines and the ou... | 07/11/2006 |
| 7074673 | Service programmable logic arrays with low tunnel barrier interpoly insulators Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and colu... | 07/11/2006 |
| 7068544 | Flash memory with low tunnel barrier interpoly insulators Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing th... | 06/27/2006 |
| 7042043 | Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ... | 05/09/2006 |
| 7027328 | Integrated circuit memory device and method Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the ch... | 04/11/2006 |
| 6952032 | Programmable array logic or memory devices with asymmetrical tunnel barriers Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain ... | 10/04/2005 |
| 6936900 | Integrated transistor devices A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulat... | 08/30/2005 |
| 6844571 | III-nitride light-emitting device with increased light generating capability The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metal... | 01/18/2005 |
| 6833556 | Insulated gate field effect transistor having passivated schottky barriers to the channel A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-s... | 12/21/2004 |
| 6479863 | Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, ... | 11/12/2002 |
| 6344659 | Superconducting transistor arrangement and a method relating thereto The present invention relates on an interferometer arrangement comprising a source electrode and a drain electrode, a base electrode to which the source electrode and the drain electrode are connected through tunnel barriers, the base electrode thus formi... | 02/05/2002 |
| 6023124 | Electron emission device and display device using the same An electron emission device exhibits a high electron emission efficiency. The device includes an electron supply layer of metal or semiconductor, an insulator layer formed on the electron supply layer, and a thin-film metal electrode formed on the insulat... | 02/08/2000 |
| 6020596 | Superconducting device including an isolation layer A FET type superconducting device comprises a substrate having a principal surface, a thin superconducting channel formed of an oxide superconductor layer over the principal surface of the substrate, a superconducting source region and a superconducting d... | 02/01/2000 |
| 5962864 | Gated resonant tunneling device and fabricating method thereof A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The f... | 10/05/1999 |
| 5717222 | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same A superconducting device includes a substrate, a projecting insulating region formed in a principal surface of the substrate, and a first thin film portion of an oxide superconductor formed on the projecting insulating region. Second and third thin film p... | 02/10/1998 |
| 5682041 | Electronic part incorporating artificial super lattice An electronic part is disclosed which is furnished with an artificial super lattice obtained by alternately superposing a substance of good conductivity formed of a compound between one element selected from among the elements belonging to the transition ... | 10/28/1997 |
| 5665979 | Coulomb-blockade element and method of manufacturing the same A Coulomb-blockade element includes a silicon layer formed on a substrate through an insulating film. The silicon layer includes a narrow wire portion and first and second electrode portions. The narrow wire portion serves as a conductive island for confi... | 09/09/1997 |
| 5621223 | Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same A superconducting device includes first and second oxide superconducting regions of a relatively thick thickness, formed directly on a principal surface of a substrate to be separate from each other, and a third oxide superconducting region of an extremel... | 04/15/1997 |
| 5594257 | Superconducting device having a superconducting channel formed of oxide superconductor material and method for manufacturing the same A superconducting device comprises a substrate having a principal surface, a non-superconducting oxide layer having a similar crystal structure to that of an oxide superconductor formed on the principal surface, which can compensates the lattice mismatch ... | 01/14/1997 |
| 5552374 | Oxide superconducting a transistor in crank-shaped configuration A superconducting device comprises a thin superconducting channel formed of an oxide superconductor, a superconducting source region and a superconducting drain region formed of an oxide superconductor at the both ends of the superconducting channel which... | 09/03/1996 |
| 5550389 | Superconducting device A superconducting device low in power dissipation and high in operating speed is fabricated by use of a combination of a superconductor material and a semiconductor material. The superconducting device having a low power dissipation and high operating spe... | 08/27/1996 |