Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 8039902 | Semiconductor devices having Si and SiGe epitaxial layers Semiconductor devices include a substrate having first and second active regions; a P-channel transistor associated with the first active region and including at least one of source and drain regions; an N-channel field-effect transistor associated with the second a... | 10/18/2011 |
| 7939896 | SOI substrate contact with extended silicide area A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon lay... | 05/10/2011 |
| 7928515 | Semiconductor device and manufacturing method of the semiconductor device A semiconductor device includes a dual gate CMOS logic circuit having gate electrodes with different conducting types and a trench capacitor type memory on a same substrate includes a trench of the substrate for the trench capacitor, a dielectric film formed in the ... | 04/19/2011 |
| 7911004 | Semiconductor device and manufacturing method of the same A semiconductor device includes a gate electrode line provided to extend from an N-type area through a device isolation area to a P-type area, and source/drain diffused regions formed in N-type and P-type areas. The gate electrode line includes a first silicide regi... | 03/22/2011 |
| 7906815 | Increased reliability for a contact structure to connect an active region with a polysilicon line By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectiv... | 03/15/2011 |
| 7800184 | Integrated circuit structures with silicon germanium film incorporated as local interconnect and/or contact Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance ... | 09/21/2010 |
| 7737505 | Semiconductor device and method of forming the same A semiconductor device may include, but is not limited to, a single crystal silicon diffusion layer, a polycrystal silicon conductor, and a diffusion barrier layer. The diffusion barrier layer separates the polycrystal silicon conductor from the single crystal silic... | 06/15/2010 |
| 7732870 | Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which elim... | 06/08/2010 |
| 7723801 | Semiconductor device and method of fabricating the same, and nor gate circuit using the semiconductor device A semiconductor device including a semiconductor substrate having source/drain regions, a gate electrode formed on and/or over the semiconductor substrate, spacers formed against sidewalls of the gate electrode, an interlayer insulating layer formed over the semicon... | 05/25/2010 |
| 7687865 | Method and structure to reduce contact resistance on thin silicon-on-insulator device A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device. ... | 03/30/2010 |
| 7675121 | SOI substrate contact with extended silicide area A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon lay... | 03/09/2010 |
| 7629655 | Semiconductor device with multiple silicide regions A system and method for forming a semiconductor device with a reduced source/drain extension parasitic resistance is provided. An embodiment comprises implanting two metals (such as ytterbium and nickel for an NMOS transistor or platinum and nickel for a PMOS transi... | 12/08/2009 |
| 7615829 | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary ... | 11/10/2009 |
| 7612416 | Semiconductor device having a conductive portion below an interlayer insulating film and method for producing the same A semiconductor device comprising: a MIS type field effect transistor which comprises a semiconductor raised portion protruding from a substrate plane, a gate electrode extending over the semiconductor raised portion from the top onto the opposite side faces of the ... | 11/03/2009 |
| 7573106 | Semiconductor device and manufacturing method therefor A method of manufacturing a semiconductor device comprises forming a gate insulation film on a semiconductor substrate; forming a first gate electrode and a second gate electrode on the gate insulation film, the area of the second gate electrode on the surface of th... | 08/11/2009 |
| 7432559 | Silicide formation on SiGe A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and sili... | 10/07/2008 |
| 7427796 | Semiconductor device and method of manufacturing a semiconductor device A semiconductor device according to an embodiment of the present invention comprises a first transistor including: a first source layer and a first drain layer both formed in one surface of a semiconductor substrate; a first silicide layer formed on the first source... | 09/23/2008 |
| 7419913 | Methods of forming openings into dielectric material This invention includes methods of forming openings into dielectric material. In one implementation, an opening is partially etched through dielectric material, with such opening comprising a lowest point and opposing sidewalls of the dielectric material. At least r... | 09/02/2008 |
| 7405450 | Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon Semiconductor devices that include a semiconductor substrate and a gate line are provided. The gate line is on the semiconductor substrate and includes a gate insulation pattern and a gate electrode which are stacked on the substrate in the order named. A spacer is ... | 07/29/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7361583 | RF semiconductor devices and methods for fabricating the same RF semiconductor devices and methods of making the same are disclosed. In a disclosed method, a trench for defining an active region and an element isolation region is formed in a semiconductor substrate. One or more gate lines is then formed within the active regio... | 04/22/2008 |
| 7358574 | Semiconductor device having silicide-blocking layer and fabrication method thereof A semiconductor device having a silicide-blocking layer is provided. The device includes a field oxide layer defining an active region, source/drain regions in the active region of a substrate, a gate oxide layer and a gate electrode on the substrate between the sou... | 04/15/2008 |
| 7355248 | Metal oxide semiconductor (MOS) device, metal oxide semiconductor (MOS) memory device, and method of manufacturing the same A semiconductor device includes a first semiconductor layer that is formed on a first insulating layer; a second insulating layer that is formed on the first semiconductor layer; a second semiconductor layer that is formed on the second insulating layer; a first gat... | 04/08/2008 |
| 7348675 | Microcircuit fabrication and interconnection Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to elec... | 03/25/2008 |
| 7329927 | Integrated circuit devices having uniform silicide junctions Integrated circuit devices are provided including an integrated circuit substrate and a gate on the integrated circuit substrate. The gate has sidewalls. A barrier layer spacer is provided on the sidewalls of the gate. A portion of the barrier layer spacer protrudes... | 02/12/2008 |
| 7326648 | Semiconductor device and fabrication process of forming silicide layer on a polysilicon pattern by reducing thickness of metal layer before forming silicide layer on the polysilicon pattern A semiconductor device includes a substrate having first and second device regions separated from each other by a device isolation region, a first field effect transistor having a first polysilicon gate electrode and formed in the first device region, a second field... | 02/05/2008 |
| 7327001 | PMOS transistor with compressive dielectric capping layer A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. C... | 02/05/2008 |
| 7320910 | Semiconductor device Manufacturing of semiconductor device includes forming, at substrate main surface, PMOS and NMOS regions separated by PN film. Polysilicon is formed at surface. First insulating film serves as gate insulating film. Second insulating film is formed on polysilicon sur... | 01/22/2008 |
| 7300842 | Method of fabricating a mask ROM A mask ROM and fabrication method thereof are disclosed, in which a bit line is formed of a conductive material such as polysilicon, by which a device size can be minimized, and by which resistance characteristics are enhanced. ... | 11/27/2007 |
| 7297618 | Fully silicided gate electrodes and method of making the same The present invention relates to a method of selectively fabricating metal gate electrodes in one or more device regions by fully siliciding (FUSI) the gate electrode. The selective formation of FUSI enables metal gate electrodes to be fabricated on devices that are... | 11/20/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7288822 | Semiconductor structure and fabricating method thereof A semiconductor structure is disclosed, including a substrate having therein a first well of a first conductivity type and a second well of a second conductivity type, a first MOS transistor of the first conductivity type and a second MOS transistor of the second co... | 10/30/2007 |
| 7283381 | System and methods for addressing a matrix incorporating virtual columns and addressing layers A system and methods for addressing unique locations in a matrix. According to some embodiments, the system includes a plurality of uniquely addressable locations. A plurality of virtual columns that include a plurality of serially connected switch elements provide ... | 10/16/2007 |
| 7271412 | Active matrix organic light emitting device having series thin film transistor, and fabrication method therefor The series TFT comprises a semiconductor layer including a first body, a second body and a connecting portion serially connecting the first body to the second body. The first body has a first channel region and first source/drain regions positioned at both sides of ... | 09/18/2007 |
| 7265400 | Semiconductor device including field-effect transistor using salicide (self-aligned silicide) structure and method of fabricating the same An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the... | 09/04/2007 |
| 7265428 | Semiconductor device having NMOSFET and PMOSFET and manufacturing method thereof An element isolation dielectric film is formed around device regions in a silicon substrate. The device regions are an n-type diffusion region, a p-type diffusion region, a p-type extension region, an n-type extension region, a p-type source/drain region, an n-type ... | 09/04/2007 |
| 7265424 | Fin Field-effect transistor and method for producing a fin field effect-transistor A fin field effect transistor having a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. ... | 09/04/2007 |
| 7259054 | Method of manufacturing a semiconductor device that includes a process for forming a high breakdown voltage field effect transistor With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type s... | 08/21/2007 |
| 7247915 | Cobalt/nickel bi-layer silicide process for very narrow line polysilicon gate technology A silicide method for integrated circuit and semiconductor device fabrication wherein a layer of nickel is formed over at least one silicon region of a substrate and a layer of cobalt is formed over the nickel layer. The cobalt/nickel bi-layer is then annealed to tr... | 07/24/2007 |
| 7244996 | Structure of a field effect transistor having metallic silicide and manufacturing method thereof A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces... | 07/17/2007 |
