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| Number | Title | Issue Date |
| 7944000 | Semiconductor resistor, method of manufacturing the same, and current generating device using the same A method for manufacturing a semiconductor resistor includes forming a well region in a semiconductor substrate, with the well region serving as a resistive region, forming a pair of contact regions spaced apart from each other in the well region, and forming a diff... | 05/17/2011 |
| 7714394 | CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and ... | 05/11/2010 |
| 7396715 | Semiconductor device and manufacturing method of the same Patterning is performed in such a manner that an end portion fabricated of a second gate insulating film partially overlaps an end portion fabricated of a first gate insulating film. Then, a surface recovery treatment is performed in the aforementioned state where t... | 07/08/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
| 7390680 | Method to selectively identify reliability risk die based on characteristics of local regions on the wafer A method and system for selectively identifying reliability risk die based on characteristics of local regions on a wafer by computing particle sensitive yield and using the particle sensitive yield to identify reliability risk die. Specifically, a bin characteristi... | 06/24/2008 |
| RE40339 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to... | 05/27/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7329583 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 02/12/2008 |
| 7326977 | Low noise field effect transistor An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the s... | 02/05/2008 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7303949 | High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown ... | 12/04/2007 |
| 7279378 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/09/2007 |
| 7276431 | Method of fabricating isolated semiconductor devices in epi-less substrate An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does... | 10/02/2007 |
| 7268399 | Enhanced PMOS via transverse stress In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regio... | 09/11/2007 |
| 7227205 | Strained-silicon CMOS device and method The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to... | 06/05/2007 |
| 7183221 | Method of fabricating a semiconductor having dual gate electrodes using a composition-altered metal layer Fabricating a semiconductor includes depositing a metal layer outwardly from a dielectric layer and forming a mask layer outwardly from a first portion of the metal layer. Atoms are incorporated into an exposed second portion of the metal layer to form a composition... | 02/27/2007 |
| 7161199 | Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive... | 01/09/2007 |
| 7132715 | Semiconductor device having a spacer layer doped with slower diffusing atoms than substrate A semiconductor device includes a silicon substrate heavily-doped with phosphorous. A spacer layer is disposed over the substrate and is doped with dopant atoms having a diffusion coefficient in the spacer layer material that is less than the diffusion coefficient o... | 11/07/2006 |
| 7019379 | Semiconductor device comprising voltage regulator element A semiconductor device includes a heavily doped layer 25 of p-type formed in the surface of an n-type well 21, an intermediately doped layer 26 of p-type formed to adjoin and surround the heavily p-doped layer 25, and an isolation region ... | 03/28/2006 |
| 7005364 | Method for manufacturing semiconductor device The invention provides a method for manufacturing a semiconductor device with which an impurity introduction region and a positioning mark region can be formed aligned, based on a common insulating film pattern. The method for manufacturing a semiconductor device in... | 02/28/2006 |
| 6995432 | Semiconductor device having a gate oxide film with some NTFTS with LDD regions and no PTFTS with LDD regions A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent theret... | 02/07/2006 |
| 6972466 | Bipolar transistors with low base resistance for CMOS integrated circuits Complementary metal-oxide-semiconductor (CMOS) integrated circuits with bipolar transistors and methods for fabrication are provided. A bipolar transistor may have a lightly-doped base region. To reduce the resistance associated with making electrical contact to the... | 12/06/2005 |
| 6963113 | Method of body contact for SOI MOSFET A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trenc... | 11/08/2005 |
| 6946711 | Semiconductor device In a semiconductor device such as MOSFET, a single crystal semiconductor substrate is provided. An epitaxitial layer is formed on the single crystal semiconductor substrate. A p-well regions are formed on the epitaxitial layer, respectively, and n+ source... | 09/20/2005 |
| 6943411 | Semiconductor device including a low resistance wiring layer A semiconductor device can include a low resistance wiring layer (13) formed in, and extending along a base material. A number of element regions (14) are formed separate from one another, each in contact with wiring layer (13). A circuit elemen... | 09/13/2005 |
| 6924190 | Use of gate electrode workfunction to improve DRAM refresh This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with redu... | 08/02/2005 |
| 6853040 | MOS transistor and fabrication method thereof A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base ... | 02/08/2005 |
| 6833591 | Semiconductor device and method for fabricating the same A method for fabricating a semiconductor device including a step of forming an interconnection having the upper surface covered with an insulation film on a base substrate, a step of sequentially depositing an insulation film and an insulation film on the base subst... | 12/21/2004 |
| 6831330 | Method and apparatus for forming an integrated circuit electrode having a reduced contact area A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A re... | 12/14/2004 |
| 6737709 | Semiconductor device A semiconductor device suppressing the lateral diffusion of impurities doped in a PMOS and NMOS and shortening the distance between the PMOS and NMOS to reduce the size of the semiconductor device, including PMOS and NMOS formation regions isolated by an element iso... | 05/18/2004 |
| 6734496 | Semiconductor device A semiconductor device has a drift region in which a drift current flows if it is in the ON mode and which is depleted if it is in the OFF mode. The drift region is formed as a structure having a plurality of first conductive type divided drift regions and a plurali... | 05/11/2004 |
| 6649983 | Vertical bipolar transistor formed using CMOS processes A vertical bipolar transistor is described which utilizes ion implantation steps which are used to form an nMOS field effect device and a pMOS field effect device. The implantation steps form an n-well, a p-well region, a pocket base region and an emitter... | 11/18/2003 |
| 6566756 | Semiconductor device with porous interlayer film of a range of average diameter having partially closed holes In a method of manufacturing a semiconductor device, semiconductor circuit elements or wiring patterns are formed on a semiconductor substrate. Then, a porous semiconductor oxide film is formed as an interlayer insulating film on the semiconductor substra... | 05/20/2003 |
| 6563173 | Silicon-on-insulator chip having an isolation barrier for reliability An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above ... | 05/13/2003 |
| 6563159 | Substrate of semiconductor integrated circuit Provided is a substrate of a semiconductor integrated circuit which can easily manufacture an integrated circuit having a soft error resistance, a latch up resistance and an ESD resistance increased. A thickness of a semiconductor surface layer having a l... | 05/13/2003 |
| 6559486 | Etching mask, process for forming contact holes using same, and semiconductor device made by the process An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3 N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, ... | 05/06/2003 |
| 6552401 | Use of gate electrode workfunction to improve DRAM refresh This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be se... | 04/22/2003 |
| 6507080 | MOS transistor and fabrication method thereof A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P... | 01/14/2003 |
| 6500714 | Method and structure for manufacturing ROMs in a semiconductor process In a traditional ROM semiconductor process, ROM codes are performed by ion implantation. Due to the limitations of ion implantation energy and threshold control, the implantation for program codes must be performed before forming an inter-layer oxide laye... | 12/31/2002 |
