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| Number | Title | Issue Date |
| 8148784 | Semiconductor device having first and second device isolation layers formed of different insulation materials A semiconductor device comprising a trench device isolation layer and a method for fabricating the semiconductor device are disclosed. The method comprises forming a plurality of first trenches on a first region of a semiconductor substrate, filling the first trench... | 04/03/2012 |
| 8102008 | Integrated circuit with buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substr... | 01/24/2012 |
| 8058692 | Multiple-gate transistors with reverse T-shaped fins A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial s... | 11/15/2011 |
| 8035168 | Elevation of transistor channels to reduce impact of shallow trench isolation on transistor performance Roughly described, transistor channel regions are elevated over the level of certain adjacent STI regions. Preferably the STI regions that are transversely adjacent to the diffusion regions are suppressed, as are STI regions that are longitudinally adjacent to N-cha... | 10/11/2011 |
| 8022481 | Robust shallow trench isolation structures and a method for forming shallow trench isolation structures In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the ... | 09/20/2011 |
| 8018006 | Semiconductor device having an enlarged space area surrounding an isolation trench for reducing thermal resistance and improving heat dissipation A semiconductor device includes a lower substrate, a thin semiconductor layer and an insulating layer formed between the lower substrate and the semiconductor layer. An active transistor area is formed with a base formed along a surface of the semiconductor layer, a... | 09/13/2011 |
| 7999328 | Isolation trench having first and second trench areas of different widths A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of t... | 08/16/2011 |
| 7994587 | Semiconductor device and semiconductor device manufacturing method A semiconductor device includes a plurality of first MOS transistors has a first gate electrode formed on a first gate insulating film provided on a semiconductor substrate, a plurality of second MOS transistors has a second gate electrode formed on a second gate in... | 08/09/2011 |
| 7968948 | Trench isolation structure in a semiconductor device and method for fabricating the same A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewa... | 06/28/2011 |
| 7932565 | Integrated circuit structure having bottle-shaped isolation An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle port... | 04/26/2011 |
| 7902611 | Integrated circuit well isolation structures An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to incre... | 03/08/2011 |
| 7872314 | Method of manufacturing semiconductor device carrying out ion implantation before silicide process An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drai... | 01/18/2011 |
| 7872313 | Semiconductor device having an expanded storage node contact and method for fabricating the same A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a y... | 01/18/2011 |
| 7847358 | High performance strained CMOS devices A semiconductor structure formed on a substrate and process for preventing oxidation induced stress in a determined portion of the substrate. The structure includes an n-FET device and a p-FET device, and a shallow trench isolation having at least one overhang is se... | 12/07/2010 |
| 7821077 | Semiconductor device The active region of an NMOS transistor and the active region of a PMOS transistor are divided by an STI element isolation structure. The STI element isolation structure is made up of a first element isolation structure formed so as to include the interval between b... | 10/26/2010 |
| 7812403 | Isolation structures for integrated circuit devices An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation r... | 10/12/2010 |
| 7808052 | Semiconductor device and method of forming the same A semiconductor device may include, but is not limited to, first and second well regions, and a well isolation region isolating the first and second well regions. The first and second well regions each may include an active region, a device isolation groove that def... | 10/05/2010 |
| 7791145 | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices ... | 09/07/2010 |
| 7768073 | Memory array buried digit line A method of forming a buried digit line is disclosed. Sacrificial spacers are formed along the sidewalls of an isolation trench, which is then filled with a sacrificial material. One spacer is masked while the other spacer is removed and an etch step into the substr... | 08/03/2010 |
| 7750413 | Semiconductor device and method for manufacturing same An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip. MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A... | 07/06/2010 |
| 7737504 | Well isolation trenches (WIT) for CMOS devices A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical ... | 06/15/2010 |
| 7723800 | Deep trench isolation for power semiconductors An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure bet... | 05/25/2010 |
| 7719061 | Flash memory device and method of fabricating the same A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral reg... | 05/18/2010 |
| 7701016 | Semiconductor device having device characteristics improved by straining surface of active region and its manufacture method A trench is formed in the surface layer of a semiconductor substrate, surrounding an active region. A lower insulating film made of insulating material fills a lower region of the trench. An upper insulating film fills a region of the trench above the lower insulati... | 04/20/2010 |
| 7696582 | Semiconductor device A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the sem... | 04/13/2010 |
| 7696581 | Isolation film in semiconductor device and method of forming the same The present invention relates to an isolation film in a semiconductor device and method of forming the same. An isolation film is formed in a doped region of a peripheral region, in which the doped region is isolated from a deep well region of a cell region and the... | 04/13/2010 |
| 7626234 | Semiconductor device with shallow trench isolation and its manufacture method A semiconductor device manufacturing method includes the steps of: (a) forming a stopper layer for chemical mechanical polishing on a surface of a semiconductor substrate; (b) forming an element isolation trench in the stopper layer and the semiconductor substrate; ... | 12/01/2009 |
| 7622778 | Semiconductor device having shallow trench isolation structure comprising an upper trench and a lower trench including a void In one embodiment, a semiconductor device has an active region defined by an isolation layer formed inside an STI trench that includes an upper trench and a lower trench having a substantially curved cross-sectional profile under the upper trench so that the lower t... | 11/24/2009 |
| 7592676 | Semiconductor device with a transistor having different source and drain lengths A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusio... | 09/22/2009 |
| 7569895 | Semiconductor device A semiconductor device having a bipolar transistor improved with heat dissipation. A semiconductor device having bipolar transistors formed in a plurality of device forming regions electrically isolated from each other by device isolation trenches traversing the sem... | 08/04/2009 |
| 7557415 | Trench isolation type semiconductor device and related method of manufacture A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing th... | 07/07/2009 |
| 7521763 | Dual stress STI The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transisto... | 04/21/2009 |
| 7504697 | Rotational shear stress for charge carrier mobility modification A semiconductor structure and its method of fabrication utilize a semiconductor substrate having an active region mesa surrounded by an isolation trench. A first isolation region having a first stress is located in the isolation trench. A second isolation region hav... | 03/17/2009 |
| 7456479 | Method for fabricating a probing pad of an integrated circuit chip A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film.... | 11/25/2008 |
| 7436030 | Strained MOSFETs on separated silicon layers A method of fabricating and a structure of an IC incorporating strained MOSFETs on separated silicon layers are disclosed. N-channel field effect transistors (nFET) and P-channel FETs (pFET) are formed on the separated silicon layers, respectively. Shallow trench in... | 10/14/2008 |
| 7436023 | High blocking semiconductor component comprising a drift section A semiconductor component having a drift path (2) which is formed in a semiconductor body (1), is composed of a semiconductor material of first conductance type. The drift path (2) is arranged between at least one first and one second electrode ... | 10/14/2008 |
| 7417298 | High voltage insulated-gate transistor An insulated-gate transistor, includes a semiconductor material layer having a front surface, a body region, an insulated gate disposed over the body region with interposition of a gate dielectric, and a source and drain region, the source region formed in the body ... | 08/26/2008 |
| 7408229 | Structure and method for accurate deep trench resistance measurement A test structure for implementing resistance measurement of a deep trench formed in a semiconductor device includes a deep trench formed within a semiconductor substrate. The deep trench has a dielectric material formed on upper portions of sidewall surfaces thereof... | 08/05/2008 |
| 7394136 | High performance semiconductor devices fabricated with strain-induced processes and methods for making same A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or m... | 07/01/2008 |
| 7394156 | Semiconductor integrated circuit device and method of producing the same A semiconductor integrated circuit device has a plurality of CMOS-type base cells arranged on a semiconductor substrate and m wiring layers, and gate array type logic cells are composed of the base cells and the wiring layers. Wiring within and between the logic cel... | 07/01/2008 |
