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"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 8072032 | Semiconductor integrated circuit device having latchup preventing function Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N1 and PchMOSFET P1 form a CMOS circuit including: NchMOSFET N2 whose gate, drain and back gate are connected to back gate of N1 and PchMO... | 12/06/2011 |
| 8022480 | Semiconductor device and method for manufacturing the same Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors. The first conducti... | 09/20/2011 |
| 7855420 | Structure for a latchup robust array I/O using through wafer via A design structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the substrate toward a top surface of the substrate... | 12/21/2010 |
| 7812402 | Semiconductor device In the upper surface of a p− substrate, an n-type impurity region is formed. In the upper surface of the n-type impurity region, a p-well is formed. Also in the upper surface of the n-type impurity region, a p+-type source region and a p... | 10/12/2010 |
| 7804138 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 09/28/2010 |
| 7741681 | Latchup robust array I/O using through wafer via A structure and a method for preventing latchup. The structure including: an I/O cell and an ESD protection circuit in a region of an integrated circuit chip containing logic circuits; an electrically conductive through via extending from a bottom surface of the sub... | 06/22/2010 |
| 7723799 | Semiconductor device A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low volt... | 05/25/2010 |
| 7675120 | Integrated circuit having a multipurpose resistor for suppression of a parasitic transistor or other purposes A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from ... | 03/09/2010 |
| 7655985 | Methods and semiconductor structures for latch-up suppression using a conductive region Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls b... | 02/02/2010 |
| 7629654 | Buried guard ring structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/08/2009 |
| 7615828 | CMOS devices adapted to prevent latchup and methods of manufacturing the same In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of ... | 11/10/2009 |
| 7541652 | Substrate coupled noise isolation for integrated circuits An integrated circuit includes a substrate, a noise sensitive circuit, and a first low impedance guard ring. The substrate includes a well-doped blocking ring that at least partially surrounds the noise sensitive circuit. The noise sensitive circuit is fabricated on... | 06/02/2009 |
| 7442996 | Structure and method for enhanced triple well latchup robustness Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues betwe... | 10/28/2008 |
| 7429771 | Semiconductor device having halo implanting regions A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semicon... | 09/30/2008 |
| 7402859 | Field effect semiconductor switch and method for fabricating it A field effect semiconductor comprises a semiconductor layer having a surface, a first and a second semiconductor region in the semiconductor layer, which are arranged next to one another at the surface of the semiconductor layer, an insulating layer between the fir... | 07/22/2008 |
| 7391200 | P-channel power chip An integrated circuit device for delivering power to a load includes a P-MOS power transistor, an N-MOS bypass transistor and a gate driver circuit. The P-MOS power transistor is coupled between a supply voltage node and a power output node of the integrated circuit... | 06/24/2008 |
| 7391069 | Semiconductor device and manufacturing method thereof In a conventional semiconductor device, for example, a MOS transistor, there is a problem that a parasitic transistor is prone to be operated due to an impurity concentration in a back gate region and a shape of diffusion thereof. In a semiconductor device of the pr... | 06/24/2008 |
| 7388260 | Structure for spanning gap in body-bias voltage routing structure Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire. ... | 06/17/2008 |
| 7358573 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 04/15/2008 |
| 7355250 | Electrostatic discharge device with controllable holding current An electrostatic discharge (ESD) device with a parasitic silicon controlled rectifier (SCR) structure and controllable holding current is provided. A first distance is kept between a first N+ doped region and a first P+ doped region, and a second distance is kept be... | 04/08/2008 |
| 7351667 | Etching solution for silicon oxide method of manufacturing a semiconductor device using the same An etching solution for silicon oxide may be used in a process for enlarging an opening formed through a silicon oxide layer. The etching solution includes about 0.2 to about 5.0 percent by weight of a hydrogen fluoride solution, about 0.05 to about 20.0 percent by ... | 04/01/2008 |
| 7348637 | Semiconductor device and method of manufacturing the same A semiconductor device including plural CMOS transistors with first and second transistors sharing a common first gate electrode and third and fourth transistors sharing a common second gate electrode that is adjacent and parallel to the first gate electrode. The fi... | 03/25/2008 |
| 7348639 | Method for providing a deep connection to substrate or buried layer in a semiconductor device A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created ... | 03/25/2008 |
| 7342276 | Method and apparatus utilizing monocrystalline insulator A semiconductor device, including: a semiconductor material; a conductive element; and a substantially monocrystalline insulator disposed between the semiconductor material and the conductive eleme... | 03/11/2008 |
| 7334198 | Software controlled transistor body bias Software controlled body bias. A target frequency is accessed. Using software, transistor body-biasing values are determined for the target frequency in order to enhance a characteristic of a circuit. The bodies of the transistors are biased based on the body-biasin... | 02/19/2008 |
| 7332763 | Selective coupling of voltage feeds for body bias voltage in an integrated circuit device An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupl... | 02/19/2008 |
| 7329552 | Field effect transistor fabrication methods, field emission device fabrication methods, and field emission device operational methods The present invention includes field effect transistors, field emission apparatuses, thin film transistors, and methods of forming field effect transistors. According to one embodiment, a field effect transistor includes a semiconductive layer configured to form a c... | 02/12/2008 |
| 7327007 | Semiconductor device with high breakdown voltage A technique is provided which allows easy achievement of a semiconductor device with desired breakdown voltage. In a high-potential island region defined by a p impurity region, an n+ impurity region is formed in an n− semiconductor layer, an... | 02/05/2008 |
| 7326609 | Semiconductor device and fabrication method A method and apparatus for manufacturing a semiconductor device is provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is... | 02/05/2008 |
| 7326977 | Low noise field effect transistor An FET (field effect transistor) having source, drain and channel regions of a conductivity type in a semiconductor body of opposite conductivity type. The channel region is located at the lower extremity of the source and drain regions so as to be spaced from the s... | 02/05/2008 |
| 7323753 | MOS transistor circuit and voltage-boosting booster circuit To an output of an NMOS having one end connected to a power source, a capacitor and a PMOS are connected. A capacitor is connected to the output of the PMOS. The NMOS and the PMOS are turned on alternately. A pulse is applied to other end of the capacitor which is c... | 01/29/2008 |
| 7309898 | Method and apparatus for providing noise suppression in an integrated circuit A method and apparatus for improving the latchup tolerance of circuits embedded in an integrated circuit while avoiding the introduction of noise from such tolerance into the power rails. ... | 12/18/2007 |
| 7304354 | Buried guard ring and radiation hardened isolation structures and fabrication methods Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isol... | 12/04/2007 |
| 7294935 | Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide Semiconducting devices, including integrated circuits, protected from reverse engineering comprising metal traces leading to field oxide. Metallization usually leads to the gate, source or drain areas of the circuit, but not to the insulating field oxide, thus misle... | 11/13/2007 |
| 7291894 | Vertical charge control semiconductor device with low output capacitance In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer... | 11/06/2007 |
| 7282771 | Structure and method for latchup suppression A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the ... | 10/16/2007 |
| 7279791 | Semiconductor device and method of fabricating the same Provides a semiconductor that enables to suppress deformation of the opening portions due to thermal expansion and contraction and to improve production yield and reliability wiring, and a method of fabricating the same. A first conductive layer and a second conduct... | 10/09/2007 |
| 7271452 | Analog switch An analog switch has a first circuit and a second circuit. The first circuit has an NMOS and PMOS connected in series, and the second circuit has a PMOS and NMOS connected in series. The first and second circuits are provided in parallel between an input terminal an... | 09/18/2007 |
| 7271453 | Buried biasing wells in FETS A structure of a semiconductor device and method for fabricating the same is disclosed. The semiconductor structure comprises first and second source/drain regions; a channel region disposed between the first and second source/drain regions; a buried well region in ... | 09/18/2007 |
| 7268400 | Triple-well CMOS devices with increased latch-up immunity and methods of fabricating same A triple-well CMOS structure having reduced latch-up susceptibility and a method of fabricating the structure. The method includes forming a buried P-type doped layer having low resistance under the P-wells and N-wells in which CMOS transistors are formed and formin... | 09/11/2007 |
