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| Number | Title | Issue Date |
| 8178930 | Structure to improve MOS transistor on-breakdown voltage A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region ... | 05/15/2012 |
| 8110878 | Semiconductor device having a plurality of shallow wells There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate wher... | 02/07/2012 |
| 8102007 | Apparatus for trimming high-resolution digital-to-analog converter A method and apparatus for trimming a high-resolution digital-to-analog converter (DAC) utilizes floating-gate synapse transistors to trim the current sources in the DAC by providing a trimmable current source. Fowler-Nordheim electron tunneling and hot electron inj... | 01/24/2012 |
| 8053844 | Hybrid orientation scheme for standard orthogonal circuits Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orient... | 11/08/2011 |
| 8049283 | Semiconductor device with deep trench structure Disclosed herein is a semiconductor device with a deep trench structure for effectively isolating heavily doped wells of neighboring elements from each other at a high operating voltage. The semiconductor device with a deep trench structure includes a semiconductor ... | 11/01/2011 |
| 8004047 | Semiconductor devices and methods of manufacture thereof A first gate dielectric of a first transistor is disposed over a workpiece in a first region, and a second gate dielectric of a second transistor is disposed over the workpiece in a second region. The second gate dielectric comprises a different material than the fi... | 08/23/2011 |
| 7999327 | Semiconductor device, and semiconductor manufacturing method In a semiconductor substrate having a first well of a conductivity type opposite to that of the semiconductor substrate, formed on part of a main surface of the semiconductor substrate, a second well of the same conductivity type as the semiconductor substrate, form... | 08/16/2011 |
| 7982271 | Semiconductor device There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate wher... | 07/19/2011 |
| 7968947 | Semiconductor device and manufacturing process therefor This invention provides a semiconductor device that can prevent a deviation of work function by adopting a gate electrode having a uniform composition and exhibits excellent operating characteristics by virtue of effective control of a Vth. The semiconduc... | 06/28/2011 |
| 7956422 | Semiconductor device, method for fabricating the same, and transformer circuit using the same A semiconductor device, a method for fabricating the same, and a transformer circuit using the same are disclosed. The semiconductor device includes a trench metal oxide semiconductor (MOS) transistor for switching a load of current supplied from a power source, and... | 06/07/2011 |
| 7911003 | Semiconductor integrated circuit device A semiconductor integrated circuit device including a semiconductor substrate and a MOS transistor having a source diffusion region and a drain diffusion region formed in the semiconductor substrate. A well is formed in the semiconductor substrate. A back gate diffu... | 03/22/2011 |
| 7884424 | Structure of MTCMOS cell An architecture of the layout of the MTCMOS standard cell designed for low power consumption is supplemented so that the pick-up cells are included in the power line of the MTCMOS cell. Therefore, when the logic circuit is constructed using the library layout of the... | 02/08/2011 |
| 7868392 | Integrated circuit tolerant to the locking phenomenon Integrated circuit comprising doped zones (3 to 8) formed in a substrate (1, 2), forming a parasitic thyristor structure with two parasitic bipolar transistors (T1, T2), the integrated circuit comprising two metallizations ... | 01/11/2011 |
| 7863688 | Layout patterns for deep well region to facilitate routing body-bias voltage Layout patterns for the deep well region to facilitate routing the body-bias voltage in a semiconductor device are provided and described. The layout patterns include a diagonal sub-surface mesh structure, an axial sub-surface mesh structure, a diagonal sub-surface ... | 01/04/2011 |
| 7859062 | Systems and methods for integrated circuits comprising multiple body biasing domains Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of... | 12/28/2010 |
| 7843012 | CMOS transistor The CMOS transistor of the present invention includes deep halo doped regions in the substrate, which can avoid the occurrence of latch-up. In addition, the fabrication of the deep halo doped regions is integrated into the process of making the lightly doped drains ... | 11/30/2010 |
| 7821076 | Semiconductor device There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate wher... | 10/26/2010 |
| 7821075 | CMOS device with zero soft error rate A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well arc... | 10/26/2010 |
| 7816742 | Systems and methods for integrated circuits comprising multiple body biasing domains Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of... | 10/19/2010 |
| 7763946 | Semiconductor device and method for manufacturing the same A semiconductor device includes: a substrate and a p-channel MIS transistor. The p-channel MIS transistor includes: an n-type semiconductor region formed in the substrate; p-type first source and drain regions formed at a distance from each other in the n-type semic... | 07/27/2010 |
| 7759740 | Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells A deep n well capacitor. A deep n well is formed in an integrated circuit. The deep n well can be parasitically coupled to Vdd and ground. A reverse-biased diode depletion region forms between n type and p type material, creating a capacitor. The capacitor provides ... | 07/20/2010 |
| 7755147 | Semiconductor device, semiconductor system and semiconductor device manufacturing method A semiconductor device is provided with a first conductivity type semiconductor substrate (10); a voltage supplying terminal (26) arranged on the semiconductors substrate (10); one or more elements (6) which include a second conductivity ... | 07/13/2010 |
| 7750412 | Rectifier with PN clamp regions under trenches A structure that includes a rectifier is formed as follows. A trench is formed in a semiconductor region of a first conductivity type. A dielectric layer is formed along opposing sidewalls of the trench but is discontinuous along the bottom of the trench. A doped li... | 07/06/2010 |
| 7745883 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 06/29/2010 |
| 7687864 | Semiconductor integrated circuit device, and apparatus and program for designing same Disclosed are a design method and apparatus in which information regarding a cell is input, the cell having taps in a substrate surface, for supplying the potentials of respective ones of wells in which active elements are formed, and source diffusion regions in the... | 03/30/2010 |
| 7635899 | Structure and method to form improved isolation in a semiconductor device A method is disclosed for forming an STI (shallow trench isolation) in a substrate during CMOS (complementary metal-oxide semiconductor) semiconductor fabrication which includes providing at least two wells including dopants. A pad layer may be formed on a top surfa... | 12/22/2009 |
| 7615827 | Dual gate dielectric thickness devices and circuits using dual gate dielectric thickness devices Dual thickness devices and circuits using dual gate thickness devices. The devices include: one or more FETs of a first polarity and one or more FETs of a second and opposite polarity, the one or more FETs of the first polarity electrically connected to the one or m... | 11/10/2009 |
| 7612415 | Method of forming semiconductor device Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photor... | 11/03/2009 |
| 7608897 | Sub-surface region with diagonal gap regions Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described. ... | 10/27/2009 |
| 7605432 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/20/2009 |
| 7605433 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/20/2009 |
| 7602023 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/13/2009 |
| 7602024 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 10/13/2009 |
| 7592675 | Partial FinFET memory cell A semiconductor structure includes a semiconductor substrate, a planar PMOS device at a surface of the semiconductor substrate, and an NMOS device at the surface of the semiconductor substrate, wherein the NMOS device is a Fin field effect transistor (FinFET). ... | 09/22/2009 |
| 7589386 | Semiconductor device and manufacturing method thereof A semiconductor device including a first field effect transistor having a source, a first conductivity type drain, a gate, and a first conductivity type channel layer formed beneath the gate and between the source and the drain. The device also includes a first cond... | 09/15/2009 |
| 7573105 | Modular bipolar-CMOS-DMOS analog integrated circuit and power transistor technology A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each o... | 08/11/2009 |
| 7573104 | CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type Embodiments herein present device, method, etc. for a hybrid orientation scheme for standard orthogonal circuits. An integrated circuit of embodiments of the invention comprises a hybrid orientation substrate, comprising first areas having a first crystalline orient... | 08/11/2009 |
| 7541651 | Semiconductor integrated circuit A semiconductor integrated circuit has a first substrate of a first polarity to which a first substrate potential is given, a second substrate of the first polarity to which a second substrate potential different from the first substrate potential is given, and a th... | 06/02/2009 |
| 7538396 | Semiconductor device and complementary metal-oxide-semiconductor field effect transistor A semiconductor device includes a substrate, an epitaxial layer, a sinker, an active device, a first buried layer, and a second buried layer. The substrate has a first type conductivity. The epitaxial layer has a second type conductivity, and is located on the subst... | 05/26/2009 |
| 7514755 | Integrated circuit modification using well implants A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The w... | 04/07/2009 |
