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Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 7405421 | Optical integrated device The present invention provides an optical device integrating an active device with a passive device without any butt joint structure between two devices. The optical integrated device of the invention includes a GaAs substrate, first and second cladding layers, and ... | 07/29/2008 |
| 7259406 | Semiconductor optical element A semiconductor optical element having a includes an n-type GaAs buffer layer, an n-type AlGaInP cladding layer, a first InGaAsP (including zero As content)guide layer without added dopant impurities, an InGaAsP (including zero In content) active layer, a second InG... | 08/21/2007 |
| 7250648 | Ferroelectric rare-earth manganese-titanium oxides Ferroelectric rare-earth manganese-titanium oxides and methods of their manufacture. The ferroelectric materials can provide nonvolatile data storage in rapid access memory devices. ... | 07/31/2007 |
| 7167387 | Variable resistance element, method of manufacturing the element, memory containing the element, and method of driving the memory The present invention lowers a drive voltage of a RRAM, which is a promising low power consumption, high-speed memory and suppresses variations in the width of an electric pulse for realizing a same resistance change. The present invention provides a variable resist... | 01/23/2007 |
| 7163848 | Semiconductor device and manufacturing method thereof OFF current of a TFT is reduced. There is provided a semiconductor device includung: a substrate; a shielding film formed so as to be in contact with the substrate; a planarization insulating film formed on the substrate so as to cover the shielding film; and a semi... | 01/16/2007 |
| 7157731 | Semiconductor device and its manufacture In a logic area, impurities are doped into the gate electrode and the source/drain diffusion regions of a MIS transistor. Thereafter in a memory cell area, word lines are patterned, source/drain regions are formed, and contact holes are formed. Side wall spacers of ... | 01/02/2007 |
| 7084353 | Techniques for mounting a circuit board component to a circuit board A circuit board has a layer of non-conductive material, and a set of soldering pads disposed on the layer of non-conductive material. The set of soldering pads defines a common axis that extends substantially through a midline of each soldering pad. Each soldering p... | 08/01/2006 |
| 7078855 | Dielectric light device A light device includes an electron supply defining an emitter surface. A dielectric tunneling layer is disposed between the electron supply and a cathode layer. The cathode layer has at least partial photon transparency that is substantially uniform across the emit... | 07/18/2006 |
| 7026217 | Method of forming an antifuse on a semiconductor substrate using wet oxidation of a nitrided substrate A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are ... | 04/11/2006 |
| 6970383 | Methods of redundancy in a floating trap memory element based field programmable gate array A method for providing redundancy in a floating charge trap device based programmable logic device includes the steps of sensing for a predetermined amount of stored charge in a first area of a floating trap devices in a floating trap device pair, and sensing for th... | 11/29/2005 |
| 6914256 | Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically ... | 07/05/2005 |
| 6888156 | Thin film device The invention provides a thin film device where ionic crystals are epitaxially grown on a Si single crystal substrate through a proper buffer layer, and its for fabrication method. A ZnS layer is first deposited on a Si single crystal substrate. Ionic crystal thin f... | 05/03/2005 |
| 6882100 | Dielectric light device A light device includes an electron supply defining an emitter surface. A dielectric tunneling layer is disposed between the electron supply and a cathode layer. The cathode layer has at least partial photon transparency that is substantially uniform across the emit... | 04/19/2005 |
| 6878958 | Vertical cavity surface emitting laser with buried dielectric distributed Bragg reflector A vertical cavity surface-emitting laser (VCSEL) structure and related fabrication methods are described, the VCSEL comprising amorphous dielectric distributed Bragg reflectors (DBRs) while also being capable of fabrication in a single-growth process. Beginning with... | 04/12/2005 |
| 6844571 | III-nitride light-emitting device with increased light generating capability The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metal... | 01/18/2005 |
| 6833556 | Insulated gate field effect transistor having passivated schottky barriers to the channel A transistor includes a semiconductor channel disposed nearby a gate and in an electrical path between a source and a drain, wherein the channel and at least one of the source or the drain are separated by an interface layer so as to form a channel-interface layer-s... | 12/21/2004 |
| 6750477 | Static induction transistor In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by... | 06/15/2004 |
| 6710382 | Semiconductor device and method for fabricating the same A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Therea... | 03/23/2004 |
| 6670652 | Monolithically integrated E/D mode HEMT and method for fabricating the same The monolithically integrated Enhancement/Depletion mode HEMT (high-electron-mobility transistor) of the present invention comprises: a buffer layer, a channel layer, a spacer layer, a first barrier layer, a second barrier layer, a third barrier layer, an... | 12/30/2003 |
| 6525379 | Memory device, method of manufacturing the same, and integrated circuit Provided are a memory device capable of accurately reading out data, a method of manufacturing the same, and an integrated circuit. A first control electrode substantially faces a second control electrode with a conduction region and a storage region in b... | 02/25/2003 |
| 6518673 | Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-in... | 02/11/2003 |
| 6479863 | Method and apparatus for injecting charge onto the floating gate of a nonvolatile memory cell A tunneling charge injector includes a conducting injector electrode, a grid insulator disposed adjacent the conducting injector electrode, a grid electrode disposed adjacent the grid insulator, a retention insulator disposed adjacent the grid electrode, ... | 11/12/2002 |
| 6337293 | Method of forming a quantum memory element having a film of amorphous silicon A semiconductor quantum memory element is disclosed which can share the terminals easily among a plurality of memory elements and can pass a high current and which is strong against noise. In order to accomplish this a control electrode is formed so as to... | 01/08/2002 |
| 6087711 | Integrated circuit metallization with superconductor BEOL wiring The present invention discloses an integrated circuit that is wired with a high-temperature superconductive material that is superconductive at temperatures of about 70° K and above, and methods of making the integrated circuit. The front-end manufacture... | 07/11/2000 |
| 6037606 | Construction of and method of manufacturing an MIM or MIS electron source In an MIM or MIS electron source that is formed by a first conductive layer 101, an insulating layer 103 that is formed onto said first conductive layer 101, and a second conductive layer 104 that is formed onto said insulating layer 103, wherein a voltag... | 03/14/2000 |
| 6023124 | Electron emission device and display device using the same An electron emission device exhibits a high electron emission efficiency. The device includes an electron supply layer of metal or semiconductor, an insulator layer formed on the electron supply layer, and a thin-film metal electrode formed on the insulat... | 02/08/2000 |
| 6015978 | Resonance tunnel device The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etch... | 01/18/2000 |
| 5962864 | Gated resonant tunneling device and fabricating method thereof A semiconductor device comprises mutually separated first and third barrier layers interposed between the first and second patterned terminals. The device operates by the resonant tunneling of carriers from the second terminal to the first terminal. The f... | 10/05/1999 |
| 5956568 | Methods of fabricating and contacting ultra-small semiconductor devices A method of fabricating ultra-small semiconductor devices including providing a mesa on a substrate. A plurality of overlying layers of semiconductor material are grown in overlying relationship to the mesa so that a perpendicular discontinuity is produce... | 09/21/1999 |
| 5844279 | Single-electron semiconductor device A semiconductor device which includes, a substrate, an insulating layer formed on the substrate, a silicon layer having an exposed surface constituted by a Si (100) face, the silicon layer being provided with a tapered recess having a bottom at which a pa... | 12/01/1998 |
| 5760463 | Superconducting layer in contact with group III-V semiconductor layer for wiring structure A superconductor device which includes a first wiring part and a second wiring part which together form a superconductive wiring. The first wiring part is arranged onto a substrate and is made of a superconductor material. The second wiring part is made o... | 06/02/1998 |
| 5751012 | Polysilicon pillar diode for use in a non-volatile memory cell There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in... | 05/12/1998 |
| 5665978 | Nonlinear element and bistable memory device An n-type diffusion layer, an insulating layer and a first aluminum electrode are formed on a p-type silicon substrate. Fe2+ (divalent Fe) having a vacant orbit not filled with an electron is implanted into a region of the insulating layer to ... | 09/09/1997 |
| 5659179 | Ultra-small semiconductor devices having patterned edge planar surfaces Ultra-small semiconductor devices and a method of fabrication including patterning the planar surface of a substrate to form a pattern edge (e.g. a mesa) and consecutively forming a plurality of layers of semiconductor material in overlying relationship t... | 08/19/1997 |
| 5644146 | Thin film transistor A thin film transistor comprises a dielectric substrate (1), a semiconductor layer (3) of poly-crystalline silicon layer having a drain region (8), an active gate region (4, 8-0), and a source region (7) placed on said substrate (1), a drain terminal (10)... | 07/01/1997 |
| 5621223 | Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same A superconducting device includes first and second oxide superconducting regions of a relatively thick thickness, formed directly on a principal surface of a substrate to be separate from each other, and a third oxide superconducting region of an extremel... | 04/15/1997 |
| 5510628 | Deep ultraviolet photolithographically defined ultra-thin films for selective cell adhesion and outgrowth and method of manufacturing the same and devices containing the same Patterned surfaces for the selective adhesion and outgrowth of cells are useful in cell culture devices, prosthetic implants, and cell-based microsensors. Such surfaces may be prepared by a deep ultraviolet photolithographic technique.... | 04/23/1996 |
| 5464989 | Mask ROM using tunnel current detection to store data and a method of manufacturing thereof Each of the portions corresponding to the crossings of a plurality of first strip conductive layers serving as bit lines and a plurality of second strip conductive layers serving as word lines crossing the conductive layers at right angles is used as one ... | 11/07/1995 |
| 5448098 | Superconductive photoelectric switch A first type of superconductive photoelectric device is provided by a superconductive thin film located between two electrodes. The superconductive thin film is one which has a photo-conductive effect and converts from a normally conducting state to a sup... | 09/05/1995 |
| 5447907 | Superconducting device with c-axis channel and a-axis source and drain having a continuous crystal structure A superconducting device comprising a substrate having a principal surface, a superconducting source region and a superconducting drain region formed of an oxide superconductor on the principal surface of the substrate separated from each other, a superco... | 09/05/1995 |
