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| Number | Title | Issue Date |
| 8183639 | Dual port static random access memory cell layout A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node;... | 05/22/2012 |
| 8178927 | Integrated circuits having a contact structure having an elongate structure and methods for manufacturing the same In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact ... | 05/15/2012 |
| 8178928 | Intermediate structures having reduced width contact holes that are formed during manufacture of memory cells having contact structures Intermediate structures are provided that are formed during the manufacture of a memory device. These structures include first and second spaced apart gate patterns on a semiconductor substrate. A source/drain region is provided in the semiconductor substrate betwee... | 05/15/2012 |
| 8169029 | High voltage device with constant current source and manufacturing method thereof A high voltage device with constant current source and the manufacturing method thereof. The device includes a P type silicon substrate (1), an oxide layer (6), a drain metal (2), a source metal (3), a gate metal (4), a P+substrate... | 05/01/2012 |
| 8169030 | Semiconductor memory device and production method thereof In a static memory cell composed of four MOS transistors, the transistors composing a memory cell are formed on a substrate and have a drain, gate, and source arranged vertically with the gate surrounding a columnar semiconductor layer. In this memory cell, the firs... | 05/01/2012 |
| 8138551 | Semiconductor device with transistors and its manufacturing method A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate e... | 03/20/2012 |
| 8129791 | Semiconductor device having a contact plug and manufacturing method thereof There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, and a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insu... | 03/06/2012 |
| 8125034 | Graded ARC for high NA and immersion lithography A method of forming a device using a graded anti-reflective coating is provided. One or more amorphous carbon layers are formed on a substrate. An anti-reflective coating (ARC) is formed on the one or more amorphous carbon layers wherein the ARC layer has an absorpt... | 02/28/2012 |
| 8125033 | Polycrystalline silicon layer, flat panel display using the same, and method of fabricating the same A polycrystalline silicon layer, a flat panel display using the polycrystalline silicon layer, and a method of fabricating the same are provided. The polycrystalline silicon layer is formed by crystallizing a seed region of an amorphous silicon layer using a super g... | 02/28/2012 |
| 8115256 | Semiconductor device A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor includin... | 02/14/2012 |
| 8102005 | Wiring substrate, semiconductor device and manufacturing method thereof The present invention provides a method for forming a wiring having a minute shape on a large substrate with a small number of steps, and further a wiring substrate formed by the method. Moreover, the present invention provides a semiconductor device in which cost r... | 01/24/2012 |
| 8102006 | Different gate oxides thicknesses for different transistors in an integrated circuit An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated cir... | 01/24/2012 |
| 8102004 | Semiconductor device and manufacturing method thereof A semiconductor device according to an embodiment of the present invention comprises: a semiconductor substrate; a first field-effect transistor formed on the semiconductor substrate, and including a fin constituted by a semiconductor layer having source and drain r... | 01/24/2012 |
| 8093658 | Electronic device with asymmetric gate strain The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement ... | 01/10/2012 |
| 8084823 | Gate minimization threshold voltage of FET for synchronous rectification A FET device for synchronous rectification of the present invention, a FET having no body diode, the characteristics have gate minimization threshold voltage equal or over load voltage, can be achieve FET turn on, and gate minimization threshold voltage under load v... | 12/27/2011 |
| 8078998 | Integrated circuits and methods of design and manufacture thereof Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes o... | 12/13/2011 |
| 8072031 | P-channel MOS transistor and semiconductor integrated circuit device A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite side... | 12/06/2011 |
| 8067805 | Ultra shallow junction formation by epitaxial interface limited diffusion A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top... | 11/29/2011 |
| 8049279 | Semiconductor device and method for fabricating the same A semiconductor device includes a substrate of a first conductivity type, a first doped region of a second conductivity type, at least one second doped region of the first conductivity type, a third doped region of the second conductivity type, a gate structure, and... | 11/01/2011 |
| 8044468 | Semiconductor device The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET ... | 10/25/2011 |
| 8018003 | Leakage power reduction in CMOS circuits A field effect transistor includes a source region and a drain region in contact with a channel region. The source and drain regions are formed in insulating pockets that cause the source and drain regions to be electrically isolated from the substrate, thereby mini... | 09/13/2011 |
| 8013395 | Semiconductor device and method for fabricating the same The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a ga... | 09/06/2011 |
| 8013396 | Semiconductor component and semiconductor device A semiconductor component includes a mixed crystal layer of silicon and germanium having a first main surface, containing a III-group impurity, and having a first face orientation alone represented as a face (11N) by using N satisfying 1.2 | 09/06/2011 |
| 8008728 | Semiconductor device and manufacturing method of semiconductor device In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; an element isolation region provided in the semiconductor substrate and having an oxide layer and an oxidant-diffusion prevention layer provided on the oxide layer;... | 08/30/2011 |
| 8004042 | Static random access memory (SRAM) cell and method for forming same In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a secon... | 08/23/2011 |
| 7994581 | CMOS transistor and method of manufacturing the same In a complementary metal-oxide semiconductor (CMOS) transistor and a method of manufacturing the same, a semiconductor channel material having a first conductivity type is provided on a substrate. A first transistor having the first conductivity type and a second tr... | 08/09/2011 |
| 7994582 | Stacked load-less static random access memory device In a stacked load-less static random access memory (SRAM) device in which a pair of transmission transistors is stacked on a pair of driving transistors, the stacked load-less SRAM device includes first and second transistors arranged in first and second active regi... | 08/09/2011 |
| 7994580 | High voltage transistor with improved driving current A semiconductor device and its method of manufacture are provided. Embodiments include forming a first doped region and a second doped region. The first and second doped regions may form a double diffused drain structure as in an HVMOS transistor. A gate-side bounda... | 08/09/2011 |
| 7986012 | Semiconductor device and process for manufacturing same A semiconductor device 100 includes a first gate 210, which is formed using a gate last process. The first gate 210 includes a gate insulating film formed in a bottom surface in a first concave portion formed in the insulating film; a gate elect... | 07/26/2011 |
| 7973367 | Semiconductor device and manufacturing method thereof In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in ... | 07/05/2011 |
| 7960793 | Semiconductor device According to one embodiment, it is possible to provide a semiconductor device provided with an MIS transistor which has an effective work function being, as much as possible, suitable for low threshold operation. A CMIS device provided with an electrode having an op... | 06/14/2011 |
| 7936022 | Method and circuit for down-converting a signal Methods, systems, and apparatuses for down-converting an electromagnetic (EM) signal by aliasing the EM signal are described herein. Briefly stated, such methods, systems, and apparatuses operate by receiving an EM signal and an aliasing signal having an aliasing ra... | 05/03/2011 |
| 7932564 | Semiconductor device and method of fabricating the same A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and... | 04/26/2011 |
| 7923784 | Semiconductor device having saddle fin-shaped channel and method for manufacturing the same A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and ov... | 04/12/2011 |
| 7919819 | Interconnect components of a semiconductor device Embodiments comprise an adjusted polysilicon gate pitch to metal wire pitch relationship to improve area scalars while increasing ACLV tolerance with a fixed polysilicon gate pitch. In some embodiments, the wire pitch for at least one metallization layer is adjusted... | 04/05/2011 |
| 7911000 | Semiconductor memory device A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between... | 03/22/2011 |
| 7902608 | Integrated circuit device with deep trench isolation regions for all inter-well and intra-well isolation and with a shared contact to a junction between adjacent device diffusion regions and an underlying floating well section Disclosed are embodiments of an improved integrated circuit device structure (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) and a method of forming the structure that us... | 03/08/2011 |
| 7898036 | Semiconductor device and process for manufacturing the same A semiconductor device includes a semiconductor substrate; a gate electrode formed on the semiconductor substrate; source and drain extension regions formed in the semiconductor substrate on a first and a second side corresponding to a first sidewall surface and a s... | 03/01/2011 |
| 7880237 | Semiconductor device A semiconductor device including a SRAM cell may include a data holding unit including a driver transistor and a load transistor, and receiving and holding data; and a data transferring unit including a transfer gate transistor whose source and drain are connected b... | 02/01/2011 |
| 7868389 | Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, ... | 01/11/2011 |