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| Number | Title | Issue Date |
| 8063447 | Multiple-gate transistors and processes of making same A microelectronic device includes a P-I-N (p+ region, intrinsic semiconductor, and n+ region) semiconductive body with a first gate and a second gate. The first gate is a gate stack disposed on an upper surface plane, and the second gate accesses the semiconductive ... | 11/22/2011 |
| 8044467 | Semiconductor device and method of fabricating the same A semiconductor device with reduced contact resistance between a substrate and a plug includes a gate electrode disposed over the substrate, the plug formed over the substrate at both sides of the gate electrode and having a sidewall with a positive slope, a capping... | 10/25/2011 |
| 7737502 | Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain The present invention provides a strained/SGOI structure that includes an active device region of a relaxed SiGe layer, a strained Si layer located atop the relaxed SiGe layer, a raised source/drain region located atop a portion of the strained Si layer, and a stack... | 06/15/2010 |
| 7675117 | Multi-gate field effect transistor A planar, double-gate transistor structure comprising upper and lower gate stacks that each comprises a single-phase high-K dielectric gate dielectric is disclosed. The transistor structure is particularly suitable for fully-depleted silicon-on-insulator electronics... | 03/09/2010 |
| 7671419 | Transistor having coupling-preventing electrode layer, fabricating method thereof, and image sensor having the same A transistor having an electrode layer that can reduce or prevent a coupling effect, a fabricating method thereof, and an image sensor having the same are provided. The transistor includes a semiconductor substrate and a well of a first conductivity type formed on t... | 03/02/2010 |
| 7646066 | Double gate FET and fabrication process A method of fabricating a double gate FET on a silicon substrate includes the steps of sequentially epitaxially growing a lower gate layer of crystalline rare earth silicide material on the substrate, a lower gate insulating layer of crystalline rare earth insulatin... | 01/12/2010 |
| 7646065 | Semiconductor device including fully-silicided (FUSI) gate electrodes A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region in the semiconductor substrate; a gate insulating film formed on the active region; and a gate electrode formed across the b... | 01/12/2010 |
| 7425744 | Fabricating logic and memory elements using multiple gate layers Various embodiments are directed to different methods and systems relating to design and implementation of memory cells such as, for example, static random access memory (SRAM) cells. In one embodiment, a memory cell may include a first layer of conductive material ... | 09/16/2008 |
| 7420253 | Three-gate transistor structure A transistor structure comprises a semiconductor element extending between a source zone and a drain zone, as well as three portions of gates disposed on different sides of the semiconductor element. Such a structure is especially compact and may be used as two or t... | 09/02/2008 |
| 7417288 | Substrate solution for back gate controlled SRAM with coexisting logic devices A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devic... | 08/26/2008 |
| 7411252 | Substrate backgate for trigate FET Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated fro... | 08/12/2008 |
| 7385249 | Transistor structure and integrated circuit A process for forming a conductive gate structure for a sub-0.25 MOSFET technology, has been developed. The process features a conductive gate structure defined from a composite polysilicon or amorphous layer, which in turn is obtained via a dual deposition procedur... | 06/10/2008 |
| 7319261 | Integrated MOS one-way isolation coupler and a semiconductor chip having an integrated MOS isolation one-way coupler located thereon A MOS isolation coupler is formed on a semiconductor chip by a CMOS process and comprises an inductor coil for generating a magnetic field in response to an input signal applied to terminals thereof. A MAGFET having a split drain formed by respective drain portions ... | 01/15/2008 |
| 7307319 | High-voltage protection device and process A high-voltage circuit protection device includes a p-n junction in a semiconductor substrate that is spaced apart from a first electrode region by a diode region. A semiconductor layer overlies the diode region and is separated therefrom by a dielectric layer. A sh... | 12/11/2007 |
| 7282772 | Low-capacitance contact for long gate-length devices with small contacted pitch Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sectio... | 10/16/2007 |
| 7265423 | Technique for fabricating logic elements using multiple gate layers Various techniques are described which utilize multiple poly-silicon layers in the design and fabrication of various logic elements that are used in semiconductor devices. According to a specific implementation of the present invention, logic gate cell sizes and mem... | 09/04/2007 |
| 7249109 | Shielding manipulations of secret data This invention concerns a method of shielding manipulations of secret data in an authentication chip from observation. In another aspect it concerns an authentication chip for performing the method. The secret data is manipulated in non-flashing CMOS structures, in ... | 07/24/2007 |
| 7208799 | Floating body cell dynamic random access memory with optimized body geometry A semiconductor device includes a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drai... | 04/24/2007 |
| 7202521 | Silicon-oxide-nitride-oxide-silicon (SONOS) memory device and methods of manufacturing and operating the same In a silicon-oxide-nitride-oxide-silicon (SONOS) memory device, and methods of manufacturing and operating the same, the SONOS memory device includes a semiconductor layer including source and drain regions and a channel region, an upper stack structure formed on th... | 04/10/2007 |
| 7199428 | Master chip, semiconductor memory, and method for manufacturing semiconductor memory A semiconductor memory includes first to sixth ridges, an insulating layers on the first to sixth ridges, a first gate line above the first to fourth ridges, and a second gate line above the third to sixth ridges, wherein the first and sixth ridges, the insulating l... | 04/03/2007 |
| 7199434 | Magnetic field effect transistor, latch and method A split drain magnetic field effect transistor (MAGFET) includes at least one supplemental gate to exert a lateral electrical field in the channel of the MAGFET. Connection of the supplemental gate in feedback with one of the two drain contacts allows the MAGFET to ... | 04/03/2007 |
| 7196374 | Doped structure for FinFET devices A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on... | 03/27/2007 |
| 7193275 | Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonunif... | 03/20/2007 |
| 7189997 | Semiconductor device and method for manufacturing the same A semiconductor device, comprises a first electrode, a semiconductor film, a first insulating film and a second insulating film formed between the semiconductor film and the first electrode, a second electrode, and a third insulating film formed between the semicond... | 03/13/2007 |
| 7190032 | Insulated gate transistor An insulated gate transistor has a semiconductor thin film having a first main surface and a second main surface, a first gate insulating film formed on the first main surface of the semiconductor thin film, a first conductive gate formed on the first gate insulatin... | 03/13/2007 |
| 7187016 | Semiconductor device In a semiconductor device an electric field is controlled in direction or angle relative to a gate, or a channel to adjust a gain coefficient of a transistor. In some embodiments, there are provided a first gate forming a channel region in a rectangle or a parallelo... | 03/06/2007 |
| 7170137 | Semiconductor device and method of manufacturing the same A semiconductor device includes a semiconductor substrate having a first conductivity type. A pair of source/drain areas having a second conductivity type is formed on a surface of the semiconductor substrate. A gate insulating film is provided on a channel area bet... | 01/30/2007 |
| 7139216 | Semiconductor storage device having a counter cell array to store occurrence of activation of word lines A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality... | 11/21/2006 |
| 7126871 | Circuits and methods to protect a gate dielectric antifuse According to embodiments of the present invention, an antifuse circuit is operated by coupling an elevated voltage to a first terminal of an antifuse, controlling current in the antifuse with a program driver circuit coupled to a second terminal of the antifuse, and... | 10/24/2006 |
| 7115921 | Nano-scaled gate structure with self-interconnect capabilities Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically co... | 10/03/2006 |
| 7113645 | Image decompression apparatus and method In a still image decompression process, operations of respective parts of a still image decompression apparatus are controlled so as to limit the operations into those such that a decompressed image on a specific LL subband is obtained. ... | 09/26/2006 |
| 7109550 | Semiconductor fabrication process with asymmetrical conductive spacers A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that ... | 09/19/2006 |
| 7101738 | Gate dielectric antifuse circuit to protect a high-voltage transistor According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a sec... | 09/05/2006 |
| 7098122 | Method of fabricating a vertically integrated memory cell A unique cell structure for use in flash memory cell and a method of fabricating the memory cell. More particularly, a vertically integrated transistor having a pair of floating gates is fabricated within a trench in a substrate. The floating gates are fabricated us... | 08/29/2006 |
| 7078282 | Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, ... | 07/18/2006 |
| 7074657 | Low-power multiple-channel fully depleted quantum well CMOSFETs A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the upperm... | 07/11/2006 |
| 7075152 | Semiconductor storage device A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a sourc... | 07/11/2006 |
| 7061053 | Semiconductor element and semiconductor memory device using the same A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so ... | 06/13/2006 |
| 7057239 | Semiconductor device allowing modulation of a gain coefficient and a logic circuit provided with the same In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonunif... | 06/06/2006 |
| 7030458 | Gate dielectric antifuse circuits and methods for operating same A number of antifuse support circuits and methods for operating them are disclosed according to embodiments of the present invention. An external pin is coupled to a common bus line in an integrated circuit to deliver an elevated voltage to program antifuses in a pr... | 04/18/2006 |
