Did You Know...
...that power steering was invented by independent inventor Francis W. Davis? As chief engineer in the 1920s of the truck division of the Pierce Arrow Motor Car Company, he saw how hard it was to steer heavy vehicles. So that he would be able to keep the profits from his future invention, Davis left his job, rented a small engineering shop in Waltham, Mass., and developed a hydraulic power steering system that led to power steering.
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| Number | Title | Issue Date |
| 8188546 | Multi-gate non-planar field effect transistor structure and method of forming the structure using a dopant implant process to tune device drive current Disclosed are embodiments of a semiconductor structure that includes one or more multi-gate field effect transistors (MUGFETs), each MUGFET having one or more semiconductor fins. In the embodiments, a dopant implant region is incorporated into the upper portion of t... | 05/29/2012 |
| 8164145 | Three-dimensional transistor with double channel configuration A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional thre... | 04/24/2012 |
| 8129790 | HOT process STI in SRAM device and method of manufacturing A structure and method for forming SRAMs on HOT substrates with STI is described. Logic circuits may also be fabricated on the same chip with some devices on the SOI regions and other devices on the SOI regions. ... | 03/06/2012 |
| 8120115 | Tunnel field-effect transistor with gated tunnel barrier A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with p... | 02/21/2012 |
| 8110877 | Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions A contact to a source or drain region. The contact has a conductive material, but that conductive material is separated from the source or drain region by an insulator. ... | 02/07/2012 |
| 8089128 | Transistor gate forming methods and integrated circuits A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work fu... | 01/03/2012 |
| 8084822 | Enhanced stress-retention fin-FET devices and methods of fabricating enhanced stress retention fin-FET devices Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer ... | 12/27/2011 |
| 8076729 | Semiconductor device having a dual gate electrode and methods of making the same Disclosed is a method for forming a dual gate electrode of a semiconductor device, which may improve manufacturing productivity by simplifying a process of forming gate electrodes in PMOS and NMOS regions, respectively, and may provide improvement in performance by ... | 12/13/2011 |
| 8076730 | Transistor level routing System and method for transistor level routing is disclosed. A preferred embodiment comprises a semiconductor device including a first semiconductor device formed on a first active area in a substrate, the first semiconductor device having a first gate stack compris... | 12/13/2011 |
| 8039900 | Stacked semiconductor devices and methods of manufacturing the same The stacked semiconductor device includes a semiconductor substrate, a multi-layered insulation layer pattern having at least two insulation layer patterns and an opening, an active layer pattern formed on each of the insulation layer patterns, a first plug includin... | 10/18/2011 |
| 8035163 | Low-cost double-structure substrates and methods for their manufacture In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-m... | 10/11/2011 |
| 8026553 | Semiconductor memory device and manufacturing method thereof This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a... | 09/27/2011 |
| 7982268 | Dual-gate transistor and pixel structure using the same A dual-gate transistor includes a first gate formed on a substrate, a first dielectric layer covering the first gate and the substrate, a semiconductor layer formed on the first dielectric layer, first and second electrodes formed on the semiconductor layer and spac... | 07/19/2011 |
| 7982269 | Transistors having asymmetric strained source/drain portions A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drai... | 07/19/2011 |
| 7977751 | Insulated gate field effect transistor and a method of manufacturing the same Disclosed herein is an insulated gate field effect transistor including: (A) a source/drain region and a channel formation region; (B) a gate electrode formed above the channel formation region; and (C) a gate insulating film; wherein the gate insulating film is com... | 07/12/2011 |
| 7973366 | Dual-gate, sonos, non-volatile memory cells and arrays thereof Memory cells which include a semiconductor substrate having a source region and a drain region separated by a channel region; a charge-trapping structure disposed above the channel region of the semiconductor substrate; a first gate disposed above the charge-trappin... | 07/05/2011 |
| 7948037 | Multiple-gate transistor structure and method for fabricating A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, an... | 05/24/2011 |
| 7943998 | Nonvolatile memory devices having stacked structures and methods of fabricating the same A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between ... | 05/17/2011 |
| 7936021 | Semiconductor device including a fin field effect transistor and method of manufacturing the same In a fin field effect transistor (Fin FET) and a method of manufacturing the Fin FET, the Fin FET includes an active pattern inside which insulating layer patterns are formed, an isolation layer pattern enclosing a sidewall of the active pattern such that an opening... | 05/03/2011 |
| 7932563 | Techniques for improving transistor-to-transistor stress uniformity An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d... | 04/26/2011 |
| 7928512 | Semiconductor device A semiconductor device is provided herein, which includes a substrate having a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The semiconductor device further includes a first stress... | 04/19/2011 |
| 7915685 | Strained-channel fin field effect transistor (FET) with a uniform channel thickness and separate gates A semiconductor device (and method for making the same) includes a strained-silicon channel formed adjacent a source and a drain, a first gate formed over a first side of the channel, a second gate formed over a second side of the channel, a first gate dielectric fo... | 03/29/2011 |
| 7906813 | Semiconductor device having a first circuit block isolating a plurality of circuit blocks A semiconductor device, includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconduct... | 03/15/2011 |
| 7906814 | Fin field effect transistor having low leakage current and method of manufacturing the FinFET Provided is a fin field effect transistor (FinFET) having low leakage current and a method of manufacturing the same. The FinFET includes: a bulk silicon substrate; a fence-shaped body formed by patterning the substrate; an insulating layer formed on a surface of th... | 03/15/2011 |
| 7902606 | Double gate depletion mode MOSFET A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abut... | 03/08/2011 |
| 7902607 | Fabrication of local damascene finFETs using contact type nitride damascene mask Disclosed are methods for forming FinFETs using a first hard mask pattern to define active regions and a second hard mask to protect portions of the insulating regions between active regions. The resulting field insulating structure has three distinct regions distin... | 03/08/2011 |
| 7888741 | Structures with improved interfacial strength of SiCOH dielectrics and method for preparing the same A semiconductor device structure and method for manufacture includes a substrate having a top first layer; a second thin transition layer located on top of the first layer; and, a third layer located on top of the transition layer, wherein the second thin transition... | 02/15/2011 |
| 7888743 | Substrate backgate for trigate FET Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated fro... | 02/15/2011 |
| 7888742 | Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts A lateral double-gate FET structure with sub-lithographic source and drain regions is disclosed. The sub-lithographic source and drain regions are defined by a sacrificial spacer. Self-aligned metal-semiconductor alloy and metal contacts are made to the sub-lithogra... | 02/15/2011 |
| 7880236 | Semiconductor circuit including a long channel device and a short channel device A semiconductor circuit is provided that includes a short channel device, and a long channel device that is electrically isolated from the short channel device. The long channel device comprises a plurality of first gate electrodes, a first source region adjacent on... | 02/01/2011 |
| 7875934 | Semiconductor substrate with islands of diamond and resulting devices Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices formed from such a substrate. A diamond island can form part of the thermal solution for an integrated circ... | 01/25/2011 |
| 7872310 | Semiconductor structure and system for fabricating an integrated circuit chip A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first ha... | 01/18/2011 |
| 7851865 | Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure Disclosed herein are embodiments of a design structure of a multiple fin fin-type field effect transistor (i.e., a multiple fin dual-gate or tri-gate field effect transistor) in which the multiple fins are partially or completely merged by a highly conductive materi... | 12/14/2010 |
| 7838942 | Substrate solution for back gate controlled SRAM with coexisting logic devices A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devic... | 11/23/2010 |
| 7829950 | Nonvolatile semiconductor memory and method of manufacturing the same A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed... | 11/09/2010 |
| 7829951 | Method of fabricating a fin field effect transistor (FinFET) device A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a ... | 11/09/2010 |
| 7808049 | Semiconductor device In a semiconductor device, a transistor in an N-type logic region NL is covered with a tensile stress applying film and a transistor in a P-type logic region PL is covered with a compressive stress applying film. Transistors in a P-type SRAM region PS and an N-type ... | 10/05/2010 |
| 7795686 | Semiconductor device using semiconductor nanowire and display apparatus and image pick-up apparatus using the same A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, an... | 09/14/2010 |
| 7786535 | Design structures for high-voltage integrated circuits Design structures for high-voltage integrated circuits. The design structure, which is formed using a semiconductor-on-insulator (SOI) substrate, may include device structure with a semiconductor body positioned between first and second gate electrodes. The first an... | 08/31/2010 |
| 7772651 | Semiconductor-on-insulator high-voltage device structures, methods of fabricating such device structures, and design structures for high-voltage circuits High-voltage device structures, methods for fabricating such device structures using complementary metal-oxide-semiconductor (CMOS) processes, and design structures for high-voltage circuits. The planar device structure, which is formed using a semiconductor-on-insu... | 08/10/2010 |
